Description:

Industrial edge systems require deterministic, low-latency communication for real-time control. This paper explores FPGA-based hardware support, featuring a TSN Ethernet endpoint and compliance with IEEE 802.1 standards for time synchronization (802.1AS-2020 & IEEE 1588), traffic shaping (802.1Qbv), frame preemption (802.1Qbu), and stream filtering (802.1Qci). Integration with GMII PHY and AXI4-Stream ensures efficient packet handling, while the Time-Aware Scheduler and PTP synchronization guarantee precise timing. Benchmarks demonstrate sub-millisecond latency and superior flexibility compared to PLCs, making FPGA-based solutions ideal for low-latency industrial edge applications.

Level: Intermediate

Description:

When developing a system, verification often takes as long as implementation, and system level tests on target make it hard to trace issues across software, FPGA, or hardware. Because these bugs appear late in the development cycle, they are time consuming to analyze and fix.

A solution to this is to run these tests against a simulation model using cocotb, which exposes simulator signals to Python. Combined with Python’s behave package, tests can be written in human readable form, improving communication across engineering teams. We implemented glue logic, so tests interact with a common DUT interface that can be backed by a Python model, HDL simulation, or on target execution, enabling incremental development and earlier bug discovery. Human readable test cases also allow domain experts to review test intentions without programming knowledge, improving review quality and ensuring requirements are fully covered. 

In the presentation, we detail these challenges, explain the solution, show the framework integration, give usage examples, and discuss key development hurdles.

Level: Intermediate

Description:

This session explains the role of the First-Stage Boot Loader (FSBL) in the boot process of AMD embedded platforms. It covers how the FSBL initializes hardware, loads software and bitstreams, and fits into common development flows such as Vitis, PetaLinux, and Yocto. Attendees will learn how the FSBL is structured, how it can be customized for specific devices and designs, and how it behaves at runtime. Advanced topics such as multi-partition flash layouts, fallback boot mechanisms, and debugging techniques are also discussed.

Level: Intermediate

Description:

The achievements of the Yosys+nextpnr open-source FPGA CAD tools are quite remarkable. Traditionally, FPGA tools, in particular for place&route had been highly vendor specific and we now have a stable, scalable and vendor-independent bitstream compilation ecosystem that is proven for various FPGA vendors and families. The quality is so good that some smaller FPGA vendors are now using Yosys+nextpnr as the prime CAD tool suite (like CologneChip or the academic FABulous project).

The Talk will highlight some of the great achievements created with Yosys+nextpnr and what it means to build a vendor-independent flow that can scale to 500K+ LUTs. The talk will also show some interesting games we played with Yosys+nextpnr in the FABulous project, like producing FPGA clones or implementing vendor-independent Partial Reconfiguration.

Level: Intermediate

Description:

Settling on a suitable hardware platform typically happens early on in a project's lifecycle, and adaptations which go beyond changing the device size within the chosen product line are rare. The main reason for this approach is the anticipated high cost of altering IP and re-training staff on different vendor tools. This talk shares the lessons learned from implementing the very same Computer Vision project, a tabletop 3D laser scanner, on mid-range FPGA and FPGA-SoC devices of all major vendors across multiple product families.

The presentation details the specific portions and percentages of the RTL design which require porting versus those that do not, as well as the associated work effort. We examine how hardware-specific components, such as MIPI, DDR memory controllers, and CPU-FPGA interfaces, can be wrapped using the module template library of Whiznium - an Open Source framework for the model-based design of embedded and FPGA solutions. Furthermore, the discussion provides a comparative analysis of how standard-compliant or forgiving various vendor tools proved to be, while evaluating the perceived ease-of-use and speed toward achieving timing closure across different environments. Finally, the session presents a first experimental result in which an LLM was trained on this specific example and tasked with porting a different application from one platform to another by generating the corresponding Whiznium model description.

Level: Intermediate

Description:

This talk presents a unified approach to advanced geometric imaging using Altera Warp FPGA IP, demonstrating its versatility across camera, projection, and AI driven systems. We show how Warp enables real time fisheye to perspective, spherical, and cylindrical projections, supporting high precision correction for wide FOV lenses. The same pipeline powers multi camera stitching by rectifying and aligning heterogeneous sensors, and acts as an efficient pre processing stage for 3D depth reconstruction through distortion correction, rectification, and reprojection. We extend these capabilities to projector domains, enabling keystone correction and seamless multi projector stitching. Running at up to 600 MHz on Agilex devices, Warp delivers deterministic, ultra low latency transformation at resolutions up to 8K, with significant power advantages over GPU based methods. Finally, we highlight how Warp offloads geometric normalization for AI pipelines, improving throughput in real time spatial perception tasks.

Level: Intermediate

Description:

FPGA projects increasingly suffer from a form of self-inflicted complexity. As designs grow larger and more interconnected, developers often become buried in their own codebases — struggling with manual workflows, limited reuse, and long feedback cycles. Progress slows not because of hardware limitations, but because existing methodologies make it difficult to regain structure once complexity has accumulated.

This talk argues that FPGA developers need better tools to shovel their way out of this complexity. Drawing on proven methodologies from software engineering, we explore how automation, continuous integration and deployment, and package management can be applied effectively to FPGA projects. Rather than treating these practices as incompatible with hardware design, we show how they directly address common pain points such as fragile integration, late-stage bugs, and unmaintainable code. We also discuss how such approaches can coexist with traditional HDL workflows and vendor toolchains.

By adopting software-inspired methodologies, FPGA teams can stop digging themselves deeper and instead build sustainable, scalable designs that keep pace with growing project demands.

Level: Intermediate

Description:

Hardware design does not have to be hard. In this talk, we will explore the foundations of hardware description languages and discuss the advantages/disadvantages of various approaches. You will learn about DFiant HDL (DFHDL), an open-source hardware description framework that leverages a unique multi-abstraction methodology for streamlined design and verification. A live demo will show how a single source of truth targets multiple FPGA platforms and a TinyTapeout ASIC, enabling reusable and portable hardware.

Level: Intermediate

Description:

A project to integrate a low cost image sensor in FPGA is presented. It is explained why this integration is beneficial in small and medium business, with a focus on the industrial companies. Then, a quick overview of a low cost image sensor is presented: electrical interfaces, timing diagrams from a first analysis and internal registers. A possible tested and working architecture in a SoC is presented.

Level: Intermediate

Description:

This presentation reports on our experience using SpinalHDL as a hardware design framework in a real FPGA project. To evaluate the workflow, coding style, and integration aspects of SpinalHDL, we implemented a moderately complex DMA controller and used it as a practical test case. The focus of the session is not the DMA itself, but the process of building and verifying a non trivial design using SpinalHDL and its surrounding ecosystem.

Topics include structuring larger components in Scala, working with SpinalHDL’s type system and bus libraries, and defining clean boundaries to SystemVerilog modules. We also discuss simulation hooks, register map generation, and the interaction with typical FPGA toolflows. The case study provides insight into handling multi channel streaming logic, managing latency considerations, and organizing code so that it remains maintainable as the design grows.

The goal of the talk is to give engineers a realistic impression of what it looks like to adopt SpinalHDL in everyday FPGA development. Attendees will see where the framework helps, where extra care is needed, and how it compares to a traditional RTL only approach when designing mid size IP blocks.

Level: Advanced

Description:

This presentation takes a deep dive into the Arm DynamIQ™ cluster within the Agilex™ 5 Hard Processor System (HPS), with a particular focus on cache subsystem behavior. It examines the operation and interaction of the cache subsystem, and how these interactions evolve under increasing system load.

The talk explores how rising workload intensity and complex memory access patterns impact core latency, stressing the cache hierarchy and the Arm DynamIQ Shared Unit (DSU). Key architectural and system-level factors that influence latency under high-stress conditions are highlighted.

Finally, the presentation discusses practical mitigation strategies to reduce latency and jitter in such scenarios. These approaches provide guidance for achieving predictable performance in hard real-time and complex mixed-criticality applications.

Level: Intermediate

Description:

The design flow for AMD Adaptive SoCs aggregates diverse artifacts for the different targets within these devices. While embedded software is one prominent project type that needs to be conquered, there are project flavours for specific IP targets like the programmable logic using HLS, or even more compute focused elements like the Versal(TM) families with AI Engines. The AMD Vitis Unified IDE provides all underlying compilers and adds productivity tools for code entry, interactive work with the devices and also offers tooling for deployment. 

Along an Adaptive SoC design we will cover the Vitis Embedded Software Projects, which include the platform wrapping a hardware designs, an application component for Linux, or real-time or bare metal targets. We will describe an actual heterogenous design by adding kernel components, and show how to handle code versioning, simulation and interactive operation to easily achieve system integration and delivery.

Level: Beginner

Description:

This is an overview on how to connect an image sensor via MIPI CSI-2 to a PC by using CrossLinkU-NX USB 3.2 Hard-IP. On the FPGA the CSI-2 video payload will be converted to raw image data first and then converted into an RGB image by a debayer before it will be sent to the PC. To display the image data on the PC the USB Video Class (UVC) is used which makes development of additional drivers obsolete.

Level: Intermediate

Description:

Next-generation data acquisition systems are pushing well beyond the limits of traditional FPGA DSP architectures. Sampling rates of 8–10 Gsps demand massive parallelism, deterministic data movement, and real-time processing flexibility—especially when ADCs lack built-in filtering or when application-specific filtering is required.

This presentation showcases how Achronix Speedster7t® FPGAs simplify extreme-bandwidth signal processing using a purpose-built architecture that combines Machine Learning Processors (MLPs) with a high-performance 2D Network-on-Chip (NoC). Attendees will see how multi-GHz, updateable FIR filtering can be efficiently implemented using MLP blocks, while the 2D-NoC enables scalable, low-latency data movement from JESD204B/C interfaces through processing, memory, and host connectivity.

We will provide a high-level overview of the Speedster7t platform—including 100G PAM4 transceivers, PCIe Gen5, 400G Ethernet, and GDDR6 memory—and demonstrate how these features come together to accelerate high-speed data acquisition and processing with unprecedented efficiency and flexibility.

Level: Beginner

Description:

Developing IP cores for FPGAs requires efficient and error-free implementation of register interfaces, especially when using standard protocols like AXI-Lite. The open-source project hdl-registers provides a powerful solution to simplify and automate this process.

This talk demonstrates how to quickly and consistently develop an AXI-Lite-compatible IP core using hdl-registers. Instead of manually implementing register definitions in HDL and maintaining a separate software interface, hdl-registers allows a single declarative register description. From this, HDL implementation, software headers, and documentation are automatically generated, reducing effort, avoiding inconsistencies, and improving code quality.

Level: Intermediate

Description:

As modern embedded systems integrate increasingly complex workloads, ensuring deterministic real-time execution while maintaining overall system flexibility has become a critical challenge. In this joint webinar, Altera and Accelerat present a combined hardware–software approach that enables hard real-time performance on the Agilex™ 5 SoC without sacrificing the ability to run rich, non-real-time applications on the same device.

Altera will introduce the architecture and capabilities of the Agilex 5 E-Series, highlighting its heterogeneous compute resources, advanced memory hierarchy, and power-efficient performance profile.

Building on this foundation, Accelerat will detail how its CLARE Software Stack enables strict spatial and temporal isolation for real-time tasks within the SoC. Through a multi-domain execution architecture, CLARE is able to allocate a dedicated domain for real-time workloads, ensuring they remain strongly-isolated from latency- and jitter-inducing interference originating from caches, memory buses, and other micro-architectural resources shared with non-real-time tasks.

This co-designed hardware/software methodology demonstrates how you can achieve deterministic, hard real-time behavior on Agilex 5 while simultaneously leveraging some cores for general-purpose or Linux-based applications. Attendees will gain insight into best practices for partitioning workloads, configuring isolated domains, and building mixed-criticality systems that combine reliability, performance, and flexibility on a single SoC.

Level: Intermediate

Description:

This presentation introduces the new AMD EDF (Embedded Design Flow) for building embedded Linux systems, 

which is intended to replace the long-established AMD PetaLinux flow. 

While PetaLinux has been widely adopted for many years, growing system complexity and the need for more scalable and flexible build environments have revealed limitations in the existing approach. 

The AMD EDF flow is designed to overcome these limitations by providing a more modular, extensible, and Yocto-aligned development methodology.

The session compares different Yocto-based build approaches and highlights the architectural and workflow differences between PetaLinux and the EDF flow. 

Level: Intermediate

Description:

High-Level Synthesis (HLS) is a programming approach that allows developers to implement FPGA hardware using high-level languages such as C or C++, instead of writing low-level hardware description code.

It promises to significantly reduce FPGA development complexity and shorten implementation time. But in an era dominated by powerful and affordable GPUs, an important question remains: why not just use a GPU?

This lecture presents a critical case study comparing an HLS-based FPGA implementation with CPU and GPU implementations using block LU decomposition, a fundamental algorithm in numerical linear algebra. We evaluate performance (GFLOPs), latency, development effort, synthesis time, and system-level power consumption. The results highlight both the advantages and limitations of HLS-driven FPGA acceleration. Based on these findings, we discuss when FPGA acceleration is technically and economically justified—and when alternative architectures are the better choice.

Level: Intermediate

Description:

Power trees are getting more sophisticated while PCB area keeps shrinking. This session presents space-optimized PMIC modules from Monolithic Power Systems that can reduce total solution area by up to 80%, simplify implementation, and maintain high efficiency with low EMI. Beyond area reduction, we cover digital interface–based configuration and programming, robust thermal performance, and tight output-voltage regulation—requirements for modern FPGA rails.

Level: Intermediate

Description:

Radiation hardness assurance is an important step in qualifying systems for use in environments with ionizing radiation, like nuclear facilities, satellites, and high energy physics experiments. With the increased adoption of advanced wireless communication systems, radiation testing becomes ever more complex. In this presentation we want to explore a practical bottom-up methodology for testing FPGA based software defined radios under radiation. 

The most critical radiation effects on FPGAs will be introduced, including single-event-effects (SEE) and total ionizing dose effects (TID). The radiation testing methodology, and one possible practical implementation will be presented, along with selected results for two testing campaigns, exploring the radiation hardness of three automatic gain control algorithms. We will conclude by mentioning how these results can be leveraged to ensure that radiation hardness, along with performance, is a primary system design goal.

Level: Beginner

Description:

Pepper is an open-source FPGA-based rapid development board designed to accelerate secure edge and networking innovation. Built around the Altera Agilex 5 FPGA, it combines reconfigurable hardware, heterogeneous computing, high-speed Ethernet switching, and extensive connectivity including 5G, Wi-Fi, and GPIO interfaces. 

Built for performance and flexibility, it enables fast implementation of Layer 2 and Layer 3 networking solutions using pre-integrated Pantherun modules.

Unlike traditional embedded platforms, Pepper enables true hardware customization, ultra-low latency processing, and hardware-level security within an open development ecosystem. 

With hardware-accelerated packet processing and full-speed, line-rate encryption, secure networking can be implemented without sacrificing performance. 

This session demonstrates how Pepper significantly reduces development cycles, simplifies FPGA-based networking design, and enables rapid deployment of high-performance, secure communication systems.

Level: Intermediate

Description:

The newly available AMD Spartan UltraScale+ family is presented technically in this session.

The presentation is of interest both to FPGA beginners and to experienced ABC developers looking to port an existing design.

Level: Beginner

Description:

2026 might finally be the year of the Linux desktop, at least for FPGA developers! Geopolitical pressure, Microsoft's update policies, and mature open-source tooling have already steered many developers from Windows to Linux-based FPGA workflows. We will look at the motivation for migrating and the benefits that come with it. We'll examine different approaches, such as native installations, virtual machines, containerization, remote desktop, or even the Windows Subsystem for Linux. The support from different FPGA vendors will also be discussed, as well as choosing the ideal distribution and desktop environment. Example projects from real-world industry products will demonstrate the current state, and a quickstart guide will be provided, so participants can start installing Linux directly after the session.

Level: Beginner

Description:

This session gives an overview of different types of reset implementations with advantages and disadvantages. Helps to understand the impact of reset coding on design reliability and how software analyzes and reports reset path timing. In the end best practices of reset coding to avoid HW related problems will be given.

Level: Beginner

Description:

EDA tools generate masses of log messages. We have seen synthesis and implementation logs exceeding 20 MiB. How can these logs be analyzed? How can these logs be checked for certain warnings, which are considered critical in a design, but aren't considered critical by the tool vendor?

This presentation will show how to (live) post-process synthesis and implementation logs from AMD Vivado with pyEDAA.OutputFilter. Each message will be classified, colored, counted, ..., it even parses tables. The tool provides a generic data format and API for user-defined data analysis and writing user-specific rules.

As a bonus, gathered statistics like resource utilization can be visualized over time using InfluxDB/Grafana. Thus, engineers and project leads can investigate how a design grows over time or when changing versions.

Level: Beginner

Description:

As the demand for domain-specific architectures grows, FPGAs have become essential for offloading compute-intensive tasks in networking, storage, and automotive sectors. However, the "Integration Gap"—the months of engineering effort required to build reliable PCIe/DMA infrastructure, kernel drivers, and memory management—often acts as a barrier to entry. This presentation introduces the Missing Link Electronics (MLE) FPGA Full System Stack (FFSS), a pre-validated, cross-platform framework designed to eliminate architectural "plumbing" and accelerate application-specific development.

Level: Beginner

Description:

This work presents the development of a flexible Deep Processing Unit (DPU) for real-time object detection using YOLO (e.g. YOLOv4) networks, specifically designed for FPGA-based acceleration. Open-source YOLO implementations such as YOLOv4 enable hardware-oriented adaptations without proprietary dependencies.

The approach starts from FPGA-friendly YOLO variants, applying quantisation and architectural simplifications such as replacing complex activations (e.g. SiLU/Swish) with ReLU, restricting the computation to operations efficiently mappable to FPGA hardware.

The proposed DPU does not implement the neural network as a fixed hardware structure, but acts as a layer orchestrator. It schedules YOLO layers and manages data movement through DMA, dynamically loading feature maps, weights, biases and layer configuration parameters. Computation units are reused across layers, and the architecture is parametrizable, allowing the number of parallel operations per cycle to be adapted to the available FPGA resources. This enables scalability across devices by trading resource usage for throughput and frames per second.

Compared to generic FPGA AI frameworks such as Vitis-AI, this work focuses on a YOLO-specific DPU, optimising performance per resource and per watt. The project is being actively implemented and validated on FPGA, demonstrating a practical and open-source solution.

Level: Intermediate

Description:

Humanoids are shaping the future of robotics, and Lattice FPGAs are at the heart of this transformation.

Discover how low power, real-time motor control, ultra-low latency, vision acceleration, and FuSa compliance make Lattice the ideal choice for next-generation humanoid designs.

This session goes beyond theory with practical insights into motor control and industrial Ethernet.

Book now to learn how to deliver smarter, safer, and more efficient humanoid solutions that stand out in the market.

Level: Intermediate

Description:

PCIe has become the de facto high-speed interface for server-grade FPGA accelerator boards, such as Xilinx Alveo cards, enabling seamless integration with host systems for demanding computational tasks. However, its versatility, high bandwidth, and relatively straightforward FPGA implementation make it equally compelling for embedded applications, where FPGAs serve as companion chips to SoCs.

This talk explores the untapped potential of PCIe in embedded FPGA designs, bridging the gap between server accelerators and compact companion chips. In the first half, we will delve into key Intellectual Property (IP) cores for PCIe integration, including their interfaces and configuration options. We will compare performance metrics such as bandwidth and latency against integrated SoC FPGAs. Additionally, we will examine the implications for device drivers.

The second half shifts focus to advanced verification strategies tailored for PCIe-connected FPGA companion chips. We will cover practical techniques using open-source tools like Cocotb for hardware verification in Python, alongside co-simulation with QEMU to model full-system behaviour.

Level: Intermediate

Description:

Traditional HDL verification uses HDL to apply stimulus and validate responses from HDL designs. Since HDLs are not well suited for this, writing testbenches takes a lot of time.

A more efficient approach is to utilize open source Co-Simulation environments like Cocotb, enabling the HDL designer to write testbenches that cover an extensive amount of test combinations without a lot of effort and coding. Cocotb comes with a large variety of open source interface models, supports various simulators and uses Python to command those. This combination leverages the high level approach of Python with the simulation tools everyone is familiar with. 

The real potential is shown, when used with standard Python libraries to validate HDL functionality. Writing complex testbenches is just a few lines of code away. Combined with tools for registers and testbench generators reduce the time to a fully functional HDL testbench to just minutes. 

The presentation shows that the time spent on validating a HDL module, which usually takes ~50% of the design time, can be reduced to only a few minutes. 

Level: Intermediate

Description:

When should you use a HyperRAM as external memory and how to implement it in combination with a NIOS V embedded soft processor into an Agilex 3 FPGA. HyperRAM is a high-speed, self-refresh Dynamic RAM (DRAM) designed for low-pin-count, low-power, and space-constrained embedded applications, such as IoT devices, wearables, automotive dashboards, HMI panels, factory automation, ...

Level: Beginner

Description:

FPGAs with integrated ADCs and DACs enable multi-GSPS signal processing, but designing DSP systems at these data rates introduces pitfalls that are easy to underestimate. Many of these issues only become visible once parallelism, throughput, and system-level constraints are fully understood.

This presentation highlights common mistakes encountered in real high-rate RFSoC projects. On the firmware side, it addresses misconceptions around achievable converter sample rates, the practical challenges of parallel FFT implementations, and why Fmax optimization is a first-order design goal rather than an afterthought. It also covers the implications of ADC data rates that exceed DDR bandwidth, and what this means for bring-up, validation, and debugging.

On the software side, the presentation draws on practical experience using C#/.NET for SoC systems. It shows how higher-level abstractions, mature GUI and application frameworks, and built-in SIMD support help manage complexity and sustain high data rates. The talk also discusses why standard Linux interfaces such as generic-uio are often a better choice than custom kernel-space drivers in terms of maintainability and development effort.

Rather than a single deep dive, this talk provides a collection of practical lessons aimed at avoiding costly design mistakes and enabling RFSoC systems that are efficient, scalable, and debuggable in practice.

Level: Advanced

Description:

This talk describes a practical method to add fault tolerance to an FPGA-based RV32IM RISC-V processor using dual-pipeline lockstep and replay recovery. Two identical pipelines execute in cycle-level synchronization, and stage-level comparison logic detects mismatches in critical execution state. A centralized control unit enforces bounded replay or halt to block incorrect architectural updates. FPGA implementation results quantify the incremental cost of detection and recovery logic relative to simple duplication.

FPGA RTL designers and hardware architects working with RISC-V or other soft processors who are interested in integrating architectural fault detection and recovery mechanisms for safety-critical or reliability-focused systems.

Architectural fault detection and recovery for FPGA-based soft processors using dual-pipeline lockstep execution and bounded replay control.

Level: Intermediate

Description:

Industrial systems are adopting confidential computing (CC) to protect sensitive data and AI models and to meet IEC 62443. 

Most deployments today use trusted execution environments (TEEs) and confidential VMs/containers to provide hardware isolation and remote attestation in OPC UA gateways, edge analytics, and OEM data-sharing. This is a major advance, but the current wave has real risks: side-channel leakage, vendor dependent attestation, weak key release, I/O gaps around accelerators, and patch-management friction in OT.

This session will:

Map today’s CC practices to IEC 62443 FR1–FR7.

Expose the top 9 vulnerabilities in TEE-centric deployments with concrete OT examples (gateways, vision, supplier KPIs).

Share a practical mitigation checklist: attestation-gated secrets, CPU isolation/SMT off, con9dential node pools, min-TCB policies, audited TrustLists, and default-deny networking.

Present a timeline where homomorphic encryption (HE), zero-knowledge proofs (ZKP), and FPGA acceleration extend CC to cross-company analytics and cryptographic compliance proofs.

Attendees will leave with clear guidance on where CC delivers value now, and how to prepare for the next wave—TEEs as the workhorse today, HE for partner analytics in the mid term, and ZKPs for veritable trust across OEMs, suppliers, and regulators.

Level: Intermediate

Description:

Livt challenges the assumption that every application needs a CPU, firmware, an OS, and a driver stack. Instead, it enables complete applications to be implemented directly on an FPGA—making a processor an optional integration choice rather than a prerequisite. This can simplify systems, reduce latency, and improve determinism while preserving application-level structure.

Software advanced through higher-level abstractions, shared libraries, frameworks, and reusable building blocks. FPGA development still tends to stay low-level: teams build isolated abstractions, engineers solve the same problems repeatedly, and complexity scales poorly.

Livt brings software-like structure to hardware by using hardware-native semantics—explicit state machines, multiplexing, and concurrency—that map directly to HDL. It supports encapsulation, interfaces, and composition, and encourages development with packages and frameworks instead of monolithic IP. These layers can be stacked and evolved, enabling incremental growth in functionality without exponential complexity.

Livt reframes FPGA design as true application development in silicon—with or without a processor.

Level: Intermediate

Description:

Modern robotic systems require high-performance, low-latency processing to handle sensing, perception, and control in real time. Field-Programmable Gate Arrays (FPGAs) provide an efficient and flexible platform for accelerating critical robotic workloads through parallel and deterministic computation. This presentation highlights the use of FPGAs in robotics, focusing on sensor pre-processing, multi-sensor fusion, real-time video and vision processing, motion control, and acceleration of Robot Operating System (ROS) components. By offloading time-critical and compute-intensive tasks to FPGA hardware, robotic systems can achieve improved performance, reduced power consumption, and enhanced real-time responsiveness.

Level: Intermediate

Description:

This session wil go through the development flow and learn about the various capabilities of the Propel Builder & Propel SDK, making use of the Radiant software and implemented on the MACHXO4 of Lattice.

Level: Beginner

Description:

Emulation of classic 1980s CPUs, such as the Motorola MC680xx series, is currently achieved through:

(complete) software emulation on a modern processor

or

(complete) hardware emulation (RT-level) on an FPGA.

With the advent of SoC-FPGAs like the AMD Zynq devices, which combine CPU and FPGA logic in a single device and thus offer a platform for a hybrid approach to CPU emulation, another option has emerged.

This project reimplements a CPU from the 1980s in an SoC device. The following aspects are utilized:

• The CPU uses sequential code to replace large logic blocks in the hardware emulation.
• The FPGA uses hardware whose implementation would require Mach cycles.

Level: Intermediate