Description:

The recent developments and price increases in DDR4 memory significantly impact the decision to implement DDR5 or LPDDR5 EMIF interfaces on Altera Agilex low-end and mid-range product families. However, the transition to DDR5/LPDDR5 requires careful consideration of cost implications, compatibility with existing systems, and the availability of supporting components.

Level: Intermediate

Description:

Verification has become one of the biggest challenges in FPGA and ASIC development, often dominating engineering schedules and project risk. While HDL-based methodologies such as UVM, DPI C, and co-simulation continue to evolve, model-based design offers unique opportunities to accelerate early verification, improve testbench quality, and unify simulation and hardware workflows.

In this talk, we explore how MATLAB® and Simulink® integrate with HDL toolchains to support modern verification strategies. We will examine methods such as co-simulation, automatic DPI C generation, UVM component generation, FPGA-in-the-Loop (FIL), and hardware-based debugging with FPGA Data Capture and AXI Manager. Practical examples illustrate how algorithm models can serve as executable testbenches, enabling faster debugging, improved coverage, and a seamless transition from functional models to HDL verification environments.

Level: Beginner

Description:

Tired of compromising performance for power efficiency? 

This session reveals the engineering breakthroughs behind Lattice FPGAs’ industry-leading low power consumption. 

We’ll explore our unique approach, showcasing how innovations across silicon process, architecture, and design methodologies culminate in FPGAs that significantly reduce system power. 

Understand the technical advantages that empower you to design smaller, cooler, and more energy-efficient solutions, all while maintaining the high performance your applications demand.

Level: Intermediate

Description:

FPGA based products grow in scope and complexity. Designs move beyond simple glue logic. Modern systems combine high speed data converters, precise motor controllers, AI driven edge processing, and industrial vision with strict latency targets. These domains add large code bases, multiple tool flows, and long validation cycles. Manual workflows struggle under this load. 

Automation plays a central role across development and product lifecycle stages. Reproducible builds lower integration risks. Scripted tests raise coverage. Automated device programming shortens hardware validation cycles. These practices support quality driven product development. Continuous integration and delivery workflows provide the structure. Build servers run synthesis, place and route, timing analysis, and bitstream generation on every change.

CI and CD environments such as Jenkins require non interactive tools. Graphical user interfaces block automation. Command line tools deliver deterministic behavior and full scripting control. Logs, versions, and errors stay visible and traceable. Tool execution fits naturally into existing build pipelines.

This presentation focuses on command line based development with Efinix FPGA devices. Topics include text based project management, version control, scripted builds, and automated hardware programming over JTAG. Attendees gain a clear view of how to manage, code, build, and program an Efinix FPGA design without leaving the command line.

Level: Intermediate

Description:

Mobile Network Operators (MNOs) across America, Asia, and Europe have reported an increase in smishing attacks delivered

via false base stations, as documented by GSMA. These attacks rely on SMS Blasters portable rogue base stations that

impersonate legitimate 4G cells, temporarily capture nearby user equipment (UE), downgrade connections to 2G, and inject

phishing SMS messages before releasing the UE back to the legitimate network. Since these attacks bypass network side

SMS filtering and operate at the radio and signaling layers, they remain largely undetectable by traditional core network or IP-based security systems.

This talk introduces a RISC-V based cellular security hub implemented as a modular IP-based system architecture for detecting SMS Blasters, IMSI catchers, and rogue base stations. The design targets low-latency, edge

deployment and focuses on signaling-plane behavioral anomalies, rather than payload inspection.

Level: Intermediate

Description:

Verification is taking a significant portion of a project’s schedule, yet functional bugs escape into production, and schedule milestones are missed more often than achieved.   As a result, powerful verification capabilities, such as those provided by Open Source VHDL Verification Methodology (OSVVM), are necessary to improve both productivity and quality.   

OSVVM provides the VHDL community with verification capabilities that rival any other verification methodology – including SystemVerilog + UVM.   Yet OSVVM is easier.  As a result, it allows any VHDL engineer to write VHDL testbenches, test cases, and verification components for both simple unit/RTL level tests and complex, randomized full chip or system level tests.

With OSVVM you get transaction-based testing, a verification framework, verification components, self-checking tests, messaging handling, error tracking, requirements tracking, constrained random testing, scoreboards, functional coverage, co-simulation with software, test automation, scripts, and a comprehensive set of test reports.

This presentation provides a tutorial depth introduction to OSVVM.

Level: Beginner

Description:

The AMD Adaptive SoCs rely on boot control out of power on reset in the processing system. This scheme is very flexible from picking the first, typically non volatile, data source to even splitting content of the loadable design between different sources. These schemes can be used to generate a flexible architecture that allows to boot application specific scenarios depending on detected environment and enable various field update concepts.

In this talk we will present the underlying boot concepts of AMD Adaptive SoCs, distinguish default behaviour and ways to adapt this behaviour to application specific setups. This can already help to identify a reasonable field update scheme. We will visit secure and non-secure booting with its implications to such multi-boot scenarios. Further we will show, along the newest Versal Adaptive SoC family additions, how the segmented boot concept has been introduced as a convenient integrated scheme to handle such design approaches.

Level: Intermediate

Description:

Deploying neural networks on FPGAs means bridging two worlds: ML engineers who think in Python and hardware engineers who write Verilog. XiperPy closes this gap as an open-source Python HDL that generates lint-clean Verilog, VHDL, and SystemVerilog from a single Python source. Its fixed-point signal type maps directly to quantized inference—Python float() for debugging, hardware-width integers for synthesis. The DSP library provides CORDIC, NCO, and CIC as composable Python objects; yield-based processes compile to FSM states; AXI-Stream and AXI-Lite interfaces connect inference pipelines to register banks. Attendees will see how a Python-native library lets ML engineers build FPGA inference engines without learning a hardware-specific language, while producing synthesizable, vendor-portable HDL.

Level: Intermediate

Description:

Software-Defined Radios (SDR) are transforming modern communications by combining flexible RF front-ends with advanced digital signal processing. FPGAs make this possible through programmability, reconfigurability and secure processing while Lattice takes it further with ultra-low power, compact form factors and uncompromising reliability.

In this session, you will discover:

How Lattice FPGAs interface seamlessly with leading RF components. Optimized DSP and memory resources for diverse waveforms and wide frequency bands. Breakthrough thermal design for A&D applications enabling SDR operation at extreme temperatures without active cooling. Join us to learn how Lattice delivers SDR solutions that meet the toughest size, weight, power and reliability challenges in Aerospace & Defense.

Level: Intermediate

Description:

Thermal management in today’s embedded system is a high priority item as more performance was put into systems over the years. Often the systems received more performance, and the thermal management had to concentrate on getting rid of the heat generated, adding weight, engineering and manufacturing complexity and cost.

Level: Intermediate

Description:

This project demonstrates the MIPI-CSI2 video path from a camera through a frame buffer located in the on-chip SRAM. It uses the MIPI D-PHY and on-chip SRAM hard IPs, MIPI-CSI2 soft IP, and a few elements of the Altera® Video and Vision IP suite.

Level: Intermediate

Description:

PCI Express is the most popular high-speed data interface between FPGAs and CPUs that allows data transfer rates of several gigabytes per second.

This lecture presents a short introduction to PCI Express and gives valuable information how FPGAs can be used to stream data directly into memory of a Graphics Processing Unit (GPU) without using CPU main memory. The great advantage is, that modern GPUs have sophisticated processing capabilities and leave the CPU’s capabilities for other tasks. A short introduction to OpenGL and the GPU’s processing power together with a live demo will be given.

Finally the attendee will have valuable Know-how to assess the performance of a GPU and be able to know the challenges when designing such applications regarding difficulty and effort.

Level: Intermediate

Description:

Simulating a Vivado Block Design is almost impossible, despite the urgent need for verifying this huge portion of a digital design. Typical questions to answer are: Are my address ranges assigned correctly? Did the automated bits calculation (User Bits, ID Bits, ...) change the overall behavior? Are there bottlenecks in the design? Many AXI IP cores are not well documented and/or not analyzed for performance.

This presentation will show how to replace the inner parts of a block design: Mainly the PS8 Core and a PL-DDR controller IP Core with a mock. The PS8 Core will be emulated with OSVVM's AXI4 verification components using a Virtual Transaction Interface (VTI).

Essentially, the presentation will demonstrate how to drill a backdoor into a component deeply hidden in the auto generated Block Design code. 

Level: Intermediate

Description:

Automotive systems have evolved into highly connected, powerful computing platforms, with increasing demand for cybersecurity as a fundamental safety requirement. In conjunction with the long lifecycle of the automotive products, deployed cryptographic mechanisms must remain secure throughout the post-quantum era. There are many automotive use cases, such as secure boot, firmware authenticity, OTA updates, and V2X communications, where post-quantum cryptography (PQC) is essential.

This presentation discusses crypto-agile, multi-mode PQC hardware architectures implemented on FPGAs as a practical approach to automotive cyber resilience. Building on multi-algorithm PQC IP concepts, the talk focuses on automotive requirements including field upgradeability, deterministic behavior, safety coexistence, and efficient resource usage. Architectural strategies based on shared computational blocks and configurable datapaths supporting multiple PQC schemes (e.g. ML-KEM or ML-DSA), are presented. The discussion also highlights practical integration aspects, supporting long-term resilience in safety-critical vehicle SoC platforms.

Level: Intermediate

Description:

Using a waveform generator as a concrete case study, this session walks through the complete Vitis HLS flow: C simulation, RTL co-simulation, integration into a classical Vivado® project, and live verification on hardware.

The example covers AXI-Lite control registers and four AXI-Stream data interfaces.

Level: Intermediate

Description:

This project demonstrates the MIPI-CSI2 video path from a camera through a frame buffer located in the on-chip SRAM. It uses the MIPI D-PHY and on-chip SRAM hard IPs, MIPI-CSI2 soft IP, and a few elements of the Altera® Video and Vision IP suite.

Level: Advanced

Description:

Technological complexity demands methodical clarity. As the CRA and Machinery Regulation (MR) converge, the FPGA lifecycle must evolve into a unified Safety-Security ecosystem. This session provides an architectural blueprint for this transition, arguing that functional safety is impossible without robust cyber resilience. We demonstrate how dynamic risk management prioritizes decisions at both the product and pipeline levels to satisfy the proportionality principles of both regulations. We bridge the gap between RTL coding and secure software methodologies, applying rigorous traceability and toolchain qualification to ensure that security updates do not compromise safety integrity. The talk analyzes the systemic impact on multi-level supply chains and the demanding maintenance "patching" marathon, where hardware components require support far beyond five years. Participants will learn how to build a pipeline that generates engineering-grade evidence for both security audits and safety certifications, ensuring networked products remain resilient, compliant, and economically viable.

Level: Advanced

Description:

This talk takes an in-depth look inside a UVVM VVC, explaining its internal architecture and core design principles. Key concepts such as the command-based interface, command queue, command interpreter, and executor are explored in detail, along with synchronization mechanisms, transaction handling, and the interaction with Bus Functional Models (BFMs).

Building on this foundation, the presentation demonstrates how to develop custom UVVM-compliant VVCs using the official templates and generator support. Practical guidance and best practices are shared to help attendees design reusable, maintainable, and well-integrated verification components that fit seamlessly into existing UVVM-based testbenches.

The talk is aimed at FPGA developers who are already familiar with the basics of UVVM and want to move beyond using existing VVCs—gaining the confidence to understand, extend, and create their own verification components.

Level: Intermediate

Description:

Wideband SDR, radar, and EW systems are pushing toward multi-GHz instantaneous bandwidth and ultra-low latency. However, traditional SDR architectures built around external RF front ends and JESD204-based converters introduce bandwidth bottlenecks, higher latency, and increased system complexity, limiting scalability and real-time performance.

This presentation explores a shift toward Direct RF architectures enabled by next-generation RF-capable FPGAs. By integrating high-speed data converters directly into the FPGA fabric, Direct RF platforms enable RF sampling rates up to 64 GSPS, significantly simplifying the RF signal chain while improving latency, synchronization, and processing efficiency. The talk discusses architectural trade-offs, clocking and synchronization considerations, and high-speed data movement using PCIe and Ethernet interfaces. Real-world wideband SDR use cases are used to illustrate how Direct RF architectures enable scalable, coherent multi-channel systems for spectrum analysis, beamforming, and EW applications.

Level: Intermediate

Description:

AXI Performance Monitors like the one in AMD MPSoC devices offer a detailed insight into the system's performance. It can measure for example data throughput, latency and acknowledgment delays.

Unfortunately, configuration of these monitors and their internal performance counters isn't straightforward. Moreover, PetaLinux doesn't provide a complete driver and/or command line application for using this

important debugging tool.

This presentation will demonstrate how to write a matching UIO driver, a C++ abstraction layer and how to format the gathered statistics for Prometheus. Finally, the data is visualized in Grafana and correlated to the embedded system's CPU load.

This tooling helps identifying bottlenecks in the early implementation phase.

Level: Beginner

Description:

Modern embedded vision systems demand high-bandwidth sensor and video interfaces with deterministic, low-latency processing at the edge.

This presentation explores FPGA-based vision architectures supporting HDMI, SDI, SLVS-EC, and CoaXPress, including HDMI-to-SDI conversion and quad CoaXPress capture. We examine how FPGAs enable flexible interface bridging, real-time image processing, and scalable high-resolution pipelines while meeting strict power, reliability, and timing requirements.

Level: Intermediate

Description:

In the rapidly evolving landscape of Physical AI, systems must now sense and act in real time. This keynote explores how low-power FPGA architectures complement modern processing platforms by managing the increasing diversity of sensors that demand specialized handling. We will discuss the strategic shift toward intelligent offloading through advanced sensor bridging and localized AI acceleration. Furthermore, we will examine the necessity of hardware-rooted security and Post-Quantum Cryptography in ensuring that the next generation of autonomous systems remains resilient and secure in an increasingly complex threat environment.

Level: Intermediate

Description:

FPGAs offer compelling advantages for deep learning inference, combining performance, determinism, and energy efficiency. However, mapping complex neural networks to hardware often requires deep hardware expertise and long development cycles. This presentation introduces a model-based approach to deploying deep learning on FPGAs using a reusable Deep Learning Processor (DLP) architecture generated with MATLAB® tools.

The talk explains how trained neural networks are compiled, quantized, and deployed onto FPGA targets using HDL Coder, leveraging pre-built or customizable processor architectures that include convolution and fully connected engines with optimized memory interfaces. Attendees will learn how layer scheduling, data movement, and performance profiling are handled automatically within the workflow, enabling systematic exploration of accuracy–throughput trade-offs.

By separating algorithm design from hardware implementation details, this approach allows engineers to move efficiently from high-level models to synthesizable HDL and FPGA bitstreams. The presentation will be relevant to FPGA designers and system architects seeking scalable and maintainable deep learning inference solutions.

Level: Beginner

Description:

This major milestone release of the PoC-Library will add our AXI4 and AXI4-Lite interconnect components. This follows our open-source release plan for providing a full AXI4 and AXI4-Lite component ecosystem written in VHDL. All components are highly customizable and are built on top of PoC's base components like FIFOs and the memory abstraction layer.

Our presentation will give a retrospective of last year's released components and a preview what comes next.

Level: Beginner

Description:

FPGA designers encounter challenges which require deeper understanding of the design in order to optimize speed, area or power consumption. Natively, FPGA designers rely on writing high-level descriptions in HDL and let the synthesizer find the best solution based on the required optimization technique. However, the tools have many limitations, and the designer can get better results in case he is aware of various techniques and analysis methodologies. In this talk we will explore different techniques such as resource and functionality sharing to reduce area, as well as alternative algorithms to increase speed. The session will demonstrate various use cases and how to write HDL code that beat the synthesizer.

Level: Beginner

Description:

Smart vision platforms in domains such as medical robotics, industrial automation, and autonomous vehicles require robust HDR imaging to operate reliably in unconstrained environments. We present an ISP architecture that extends dynamic range by up to 30 dB, reaching 120 dB through multi exposure sensor fusion and an adaptive, content aware tone mapping method, including local tone mapping applied directly in the Bayer domain. To support HDR encoding and format conversion, we introduce an optimized 1D LUT IP for PQ/HLG transfer functions and a 3D LUT stage for color volume and gamut mapping across HDR formats. These LUT based components enable efficient companding of 20 bit signals and accurate, resource efficient interoperability between heterogeneous HDR video pipelines. The combined approach delivers a scalable, low latency solution suited to next generation intelligent cameras and embedded vision systems.

Level: Intermediate

Description:

For most FPGA and ASIC designs, using verification models/processes/components will significantly improve the testbench overview, the corner case coverage and the quality, while also reducing the development and debugging time. BUT – this does of course depend a lot on the verification component architecture and functionality. 

UVVM provides the best-in-class approach to verification components, which allows developers to implement very structured testbenches and very well controllable and understandable test sequencers – even for complex designs.

This presentation will explain why the UVVM approach is superior, show the functionality and benefits it provides, and show and explain the actual verification component architecture.

Level: Intermediate

Description:

The increasing miniaturisation of electronic assemblies significantly raises the requirements for thermal reliability and service life of modern systems. Precise and proactive thermal management is therefore essential to prevent overheating, performance losses and potential system failures. The early integration of a holistic thermal management strategy into the development process is crucial in order to counteract increasing system complexity and ensure long-term functional reliability.

Modern thermal management software enables the direct use of detailed PCB layout data from ECAD/EDA systems, taking thermal simulation to a new level of quality. By linking thermal analyses with system requirements and relevant design parameters, thermal limits can be reliably adhered to and the effects of design changes or new requirements can be specifically evaluated.

The presentation shows how development teams use modern thermal management methods to define critical temperature targets, analyse heat flows and cooling concepts, and create a consistent, efficient development environment through the integration of ECAD systems and thermal simulation software, enabling fast and reliable statements about the thermal behaviour of electronic systems.

Level: Intermediate

Description:

Safety-critical FPGA designs in domains such as automotive (ISO 26262) and industrial automation (IEC 61508) require a structured and traceable verification strategy to demonstrate compliance with safety, security, and cyber resilience regulations. Beyond functional correctness, these standards mandate evidence of verification planning, requirement coverage, traceability of results, and validation of tool confidence levels. Establishing such a verification flow early in the project is essential to manage complexity, maintain consistency across teams, and ensure audit-ready documentation throughout the lifecycle.

Siemens EDA Verification IQ (Questa VIQ) provides an integrated verification management environment built on a scalable, data-centric architecture. It aggregates verification data from multiple sources—simulation, formal analysis, coverage collection, and regression management—to form a single source of truth. Through its integration with Polarion ALM, engineers can achieve full bidirectional traceability between requirements, HDL design elements, verification plans, and results. This linkage not only enables compliance reporting but also supports impact analysis when requirements or design elements change.

This presentation demonstrates how FPGA design teams can use VIQ to define and monitor verification objectives aligned with safety standards, ensure coverage completeness with respect to requirements, and collect evidence suitable for certification audits. By embedding traceability, metrics, and accountability directly into the verification flow, VIQ helps teams meet regulatory obligations efficiently while improving overall design quality and verification confidence.

Level: Intermediate

Description:

Every PCB design has its own challenges. When an FPGA is introduced the PCB complexity increases drastically and minor or major, potentially deal-breaking, mistakes are possible.

In this talk I want to show which possibilities we have inside the FPGA to overcome real-world problems. We will start with simple things as wrong signal polarity, through line-delay mismatch up to completely misplaced transceivers.

Level: Beginner

Description available shortly

Description:

Performing a full system simulation including the ARM-based Processing System is a complex and time-consuming task. As an alternative, this session shows how a MicroBlaze V soft processor combined with C-based simulation software can be used to efficiently verify and validate the programmable logic.

Level: Intermediate

Description:

The session will quickly review the Architecture of AMD Gigabit Transceivers then we will work on a link between two boards to show how IBERT helps to troubleshoot and setup a link with optimal performance.

We will see the differences between an optical connection and a copper connection, pros, cons and possible GT setup options.

This is mainly a live demonstration.

Level: Intermediate

Description:

Co-simulating Qiskit with VHDL/Verilog represents the bridge between high-level quantum software and the low-level hardware logic required to control physical qubits.

Architectural Pathways for Qiskit-HDL Integration

To synchronize the probabilistic world of Qiskit with the deterministic world of RTL (Register Transfer Level), engineers generally use one of three frameworks:

1. Quantum Control (The Cocotb Approach)

This is the most common path for FPGA engineers. You use Cocotb (a Python-based verification framework) as the "glue."

• Mechanism: Qiskit generates the quantum instructions, and Cocotb passes these values into the HDL simulator via a Python interface.
• Use Case: Developing Quantum Control Units (QCUs) that must handle pulse timing and feedback loops.

2. Quantum Emulation (The Backend Approach)

Instead of just controlling hardware, you use hardware to mimic a quantum computer.

• Mechanism: You write a Custom Qiskit Backend. When you call backend.run(circuit), Qiskit doesn't send data to IBM; it triggers a hardware-accelerated simulation on an FPGA or an HDL simulator.
• Use Case: Testing high-speed quantum algorithms that are too slow to simulate on standard CPUs.
• 3. Quantum Verification (The Validation Approach)

This focuses on "equivalence checking."

• Mechanism: Running a circuit in Qiskit (the "Golden Model") and the same logic in an HDL environment simultaneously to ensure the hardware accurately represents the quantum gates.
• Use Case: Ensuring that a hardware-implemented CNOT gate produces the exact state vector expected by the theoretical model.
• Technical Examples
• Measurement Transfer: Converting the probability of two tangled qbuits in Qiskit into a high/low digital signal in VHDL.
• State Analysis: Using Qiskit’s visualization tools (like plot_bloch_multitask) and Riviera-PRO Plot view to display data processed by quantum logic.
• Gate Comparison: Correctness of quantum circuits against its hardware-accelerated HDL counterpart.

Level: Beginner

Description:

With the addition of the Versal AI Edge Gen2 and Versal Prime Series Gen2 to the portfolio, even more powerful feature sets are available to build demanding heterogenous designs. Foremost there is an upscaled processing system that allows a higher number of ARM cores and connectivity. But also more hardened IP is showing, partially resonating from the Zynq Ultrascale+ MPSoC, like the VCU and GPUs.

In this talk we will explore an overview of these gen 2 features available within specific devices. Insight into the tool flow will be presented from design entry to Vitis Unified IDE's platform components or EDF SDKs, where using APIs to control the items from applications. Along we will visit various architectural enhancements, including the DDR controller, IO resources, and security features. All these contribute to the Versal family to tightly integrate efficient solutions. These can be deployed readily with pre-configured images that are available for deeper dive.

Level: Intermediate

Description:

Methods for calculating roots based on Professor Töpler's historical algorithm(1866) are discussed. This algorithm only requires additions, subtractions, and shift operations, which enabled its use on historical, mechanical calculating machines.

Historically, base-10 numbes are used. However, in FPGAs a base-2 representation is meaningful.

A binary version of this square root algorithm is described, which simplifies the determination of the individual digits compared to other bases. The iteration equations for the digit-wise computation will be derived, appropriately represented in hardware blocks, and then described as a VHDL component.

Following this, the computation of the cube root will be outlined, and the associated iteration equations, block diagrams, and VHDL descriptions are presented.

The VHDL components explained have AXI stream interfaces, which allow easy integration into your own circuits.

Level: Intermediate

Description:

Humanoid robots are moving toward scalable, Ethernet-based architectures that support stereo depth perception, distributed cameras, and real-time intelligence. Microchip PolarFire® FPGAs, integrated with NVIDIA Holoscan, provide a complete solution for vision and precision motor control in next-generation humanoid systems.

We will show how to implement a power-efficient, deterministic pipeline for synchronized stereo and multi-camera vision, leveraging high-bandwidth SerDes and flexible protocol support to transport time-aligned image data over Ethernet into NVIDIA Holoscan for AI-driven perception and sensor fusion. In parallel the highly dexterous manipulators require deterministic low-latency motor control which can only be achieved using FPGAs. Talking of controlling hands, 20+ degrees of freedom may be required to deliver the precision and accuracy needed for human-like motion.

Together, the combination of FPGA and GPU offer a scalable, standards-based architecture that unifies depth perception, distributed vision, and ultra-low-latency control in power-constrained humanoid platforms.

Level: Intermediate

Description:

UVVM’s Advanced and Optimised Randomisation and Functional Coverage was developed in cooperation with ESA (European Space Agency). In UVVM, understanding and readability of these features have been taken to a new level, and UVVM also introduces functionality not previously available for VHDL testbenches. The user threshold is far lower than for SystemVerilog and makes it easy for VHDL designers to use this advanced functionality. The randomisation and coverage functionality in UVVM may of course be integrated with any other VHDL verification methodology.

This presentation will explain all of this and also discuss the use of Randomisation and Functional Coverage in general.

In the latest ESA project, there has also been a tight cooperation with Siemens to extend the UVVM randomisation and functional coverage functionality even further. This will allow the use of advanced SystemVerilog functionality directly from a pure VHDL testbench – just using slightly more advanced UVVM commands. 

This functionality will also be shown and exemplified in this presentation.

Level: Intermediate

Description:

The presentation goes to all the steps required to successfully synchronize multiple channels and multiple chips when working with AMD RF_SOC and Versal RF.

We will see the HW and SW needs, clocking architectures, troubleshoot and tuning techniques.

Level: Advanced

Description:

Building upon the previous seminar, "Simulating Big Memories using OSVVM’s Memory Model" by Patrick Lehmann and  Adrian Weiland, this session explores the technical advantages of the VHDL-2019 integer expansion.

Historically, VHDL's 32-bit integer limit forced workarounds for high-capacity memory modeling and high-frequency timing. With VHDL-2019 now mandating a minimum 64-bit range for the INTEGER type—and support already live in tools like Riviera-PRO—new simulation possibilities have emerged.

In collaboration with the PLLC2  team, we will demonstrate:

Architectural Shifts: How the transition to 64-bit integers simplifies the modeling of massive datasets and address spaces.

Practical Implementation: An inside look at the PLLC2team’s design, utilizing OSVVM models specifically adapted for the 64-bit range.

Performance Optimization: Strategic hints on improving simulation throughput and memory management in modern VHDL environments.

Level: Beginner

Description:

The physical AI grows fast with more intelligence in the form of robot that is composed of sensors, computing engine (CPU/GPU), and actuators. CPU/GPU gets raw data from sensors over high-speed network, processes, and makes high-level decisions. But, as the number of sensors increases, the low-level processing of raw data becomes a larger task that burns sizable computing resources, and the network also becomes crowded with more raw data. This becomes a limiting factor for the use of more sensors. The synchronization of actuators becomes an issue too as the number of actuators grows, while low & deterministic synchronization is needed in modern robots. Lastly, chips need to work in a tighter and enclosed area with not much air flow in robots, and it makes the heat dissipation much harder.

To tackle these issues, we are using low power FPGA. It is located near to sensors to sync, fuse, and process the data before sending over network. It reduces the computing burden of CPU/GPU so that it can do intelligent task instead of low-level computing and the network bandwidth since it sends digested data. FPGA is used for the communication for sync of actuators, and it gives deterministic & low latency compared to the MCU based solutions. Lastly, the less heat from the low power FPGA removes the need for any fan or heat sink, which is essential for a tight closed environment.

These benefits of FPGAs make robots more intelligent and work long without extra cost on CPU/GPU and battery.

Level: Intermediate

Description:

FPGA projects rarely fail because of insufficient logic resources or slow tools. They fail because of hidden methodological costs that silently consume schedules, budgets, and team energy.

This talk examines how poor FPGA development methodology creates a “hidden tax” that dramatically increases time-to-market—often long before the first line of RTL is written. Drawing from real project experience, we will explore where this tax originates: premature RTL commitment, weak system-level architecture, late verification, fragile timing strategies, misused IP, and integration-phase surprises.

We will also look at less obvious contributors such as build non-reproducibility, unclear ownership, and missing design intent. The focus is not on tools or coding style, but on process decisions that either amplify or eliminate risk. 

Attendees will leave with practical insights on how experienced teams structure FPGA projects to reduce friction, shift risk early, and ship designs on time.

Level: Beginner

Description:

This seminar compares FreeRTOS and Zephyr in the context of AMD embedded platforms and modern application demands. It explains why Zephyr is gaining momentum and how AMD supports Zephyr across ARM and RISC-V architectures. Key architectural differences, features, and development workflows are highlighted. Participants will leave with a clear understanding of when and why a migration from FreeRTOS to Zephyr makes sense.

Level: Beginner