Agenda - 7 July 2021
08:40 - 08:55 am
Opening Session with the organizers - ELEKTRONIKPRAXIS & PLC2
09:00 - 09:40 am
JESD204 Interface Framework (JIF) (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Laszlo Nagy | Analog Devices GmbH (view description)
09:45 - 10:25 am
FPGA Accelerators in 5G OpenRAN (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Felix Winterstein | Xelera Technologies GmbH (view description)
10:30 - 11:00 am
Break-Out with Partners
11:00 - 11:40 am
On the Design and Implementation of Open RAN Direct RF Sampling Radio Transceiver Architectures (45 min)
Level: Intermediate/Expert
Speaker: Sassan Ahmadi | Xilinx (view description)
11:45 am - 12:25 pm
FPGA based Time-Sensitive Networking for 5G Fronthaul – Challenges and Solutions (45 min)
Level: Beginner/Intermediate
Speaker: Silviu Adrian Sasu | ADVA Optical Networking SE (view description)
12:30 - 12:45 pm
Break
12:45 - 01:30 pm
COUCH TALK: AI Start-up culture in Europe: The situation of young AI related companies in Europe/Germany.
Do we need an open AI eco system?
Participants:
Siegfried Weigert | CEO, ibw Industry Consulting (Moderator)
Sigrid Rögner | Head of Business Innovation and Ecosystem, IDS Imaging Development Systems GmbH
Enrico Giordano | CEO/CTO, MakarenaLabs srl.
Jens Stapelfeldt | TSL & Eco-System Partner Manager Europe, Xilinx
01:30 - 02:00 pm
KEYNOTE: Reducing the risk of supply chain problems by use of FPGAs (30 min)
Speaker: Dr. Michael Gude | Cologne Chip AG (view description)
02:00 - 02:40 pm
Synthesizing Dataflow Designs from a High-Level Description (45 min)
Level: Intermediate
Speaker: Richard Membarth (view abstract) & Puya Amiri | DFKI (view description)
02:45 - 03:25 pm
Creating FPGA-based low-power vision-designs in C/C++ using SmartHLS (45 min)
Level: Beginner/Intermediate
Speaker: Andrew Canis and Jens Huettemann | Microchip Technology GmbH (view description)
03:30 - 04:00 pm
Break-Out with Partners
04:00 - 04:40 pm
Optimizing an FPGA-based OpenCL AI Kernel for the Data Center (45 min)
Level: Intermediate
Speaker: Pantelis Sarais | SILEXICA GmbH (view description)
04:45 - 05:25 pm
FPGA Based Fronthaul and High-PHY acceleration for 5G Networks (45 min)
Level: Intermediate
Speaker: Awanish Verma | Xilinx (view description)
05:30 pm
Closing Session
08:40 - 08:55 am
Opening Session with the organizers - ELEKTRONIKPRAXIS & PLC2
09:00 - 09:40 am
Vitis for Acceleration – Creating a RTL Kernel: from HDL to reusable packaged Kernel (45 min)
Level: Intermediate
Speaker: Alexander Flick | PLC2 GmbH (view description)
09:45 - 10:25 am
Accelerated Vitis Libraries for Smart Vision (45 min)
Level: Beginner/Intermediate
Speaker: Stanislaw Klinke | EBV Elektronik GmbH & Co. KG (view description)
10:30 - 11:00 am
Break-Out with Partners
11:00 - 11:40 am
Versal – Adaptable Compute Acceleration Platform in Vitis(45 min)
Level: Beginner/Intermediate
Speaker: Alexander Flick | PLC2 GmbH (view description)
11:45 am - 12:25 pm
Moving AXI Interconnects from PL to the NOC (45 min)
Level: Intermediate
Speaker: Ernst Wehlage | PLC2 GmbH (view description)
12:30 - 12:45 pm
Break
12:45 - 01:30 pm
COUCH TALK: AI Start-up culture in Europe: The situation of young AI related companies in Europe/Germany.
Do we need an open AI eco system?
Participants:
Siegfried Weigert | CEO, ibw Industry Consulting (Moderator)
Sigrid Rögner | Head of Business Innovation and Ecosystem, IDS Imaging Development Systems GmbH
Enrico Giordano | CEO/CTO, MakarenaLabs srl.
Jens Stapelfeldt | TSL & Eco-System Partner Manager Europe, Xilinx
01:30 - 02:00 pm
KEYNOTE: Reducing the risk of supply chain problems by use of FPGAs (30 min)
Speaker: Dr. Michael Gude | Cologne Chip AG (view description)
02:00 - 02:40 pm
GateMate FPGA Synthesis with Third-Party Tools (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Patrick Urban | Cologne Chip AG (view description)
02:45 - 03:25 pm
Lattice ICE40UP FPGAs (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Eugen Krassin | Krassin Consulting GmbH (view description)
03:30 - 04:00 pm
Break-Out with Partners
04:00 - 04:40 pm
FRACTAL – Introduction to a cognitive edge platform (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Alexander Flick | PLC2 GmbH (view description)
04:45 - 05:25 pm
FPGA-Based Deep Learning (DEEP Neural Networks) Inference Accelerator (45 min)
Level: Beginner
Speaker: Robin Chacko | PLC2 Design GmbH (view description)
05:30 pm
Closing Session
