Lecture Description:

The ARM based Bus Architecture standard of AXI defined the hardware interconnect standard AXI4 and Xilinx provides a huge range of AXI4 based IPs including bridging solutions. For very high throughput demands the resource utilization is getting critical high and is also limited by with its clock rate to fulfill timing closure. The next generation family Xilinx Versal ACAP brings this interconnect network into a silicon block which is the NoC (network-on-chip). NoC provides 1 GHz clock rates higher and that guaranteed timing closure in the interconnect architecture. In this session you’ll lean to understand the NoC and we demonstrate how to move a programmable logic AXI interconnect onto the NoC.