Lecture Description:

In this talk, we present a new approach to generate dataflow-style hardware designs from a high-level description in a functional programming language that offers explicit partial evaluation.
This approach allows the programmer to focus on describing the algorithmic stages of streaming applications with no need to define the dataflow structure. The compiler will detect the dataflow inherent to the application and generate efficient pipelined streaming hardware designs accordingly. In particular, our generated dataflow designs will enable burst transfers for Xilinx Vitis. The generated code is accompanied by corresponding host code to launch the application via Xilinx XRT. Besides, the compiler is able to provide OpenCL code for both Intel and Xilinx FPGAs. We demonstrate our framework using image processing applications and compare to state-of-the-art approaches.