Lecture Description:

The GateMate Series is the latest FPGA development for small to medium-sized programmablelogic applications. Its architecture relies on flexibly configurable logic blocks with more in- and
outputs than usual and a novel approach to routing between logic blocks. It is the first FPGA to be developed and produced in Europe.
Software plays one of the most important roles in developing applications for FPGAs. Today's development environments are mostly dominated by commercial tools. A FPGA manufacturer is
faced with the question of whether to support proprietary or open source tools. For this purpose we have investigated various industrial standard tools such as Cadence Genus, Leonardo Spectrum, but also open source solutions such as the Yosys Open Synthesis Suite1. We extended it with a synth_gatemate pass to synthesize Verilog code to the Gatemate architecture - including logic
gates, registers, RAM cells and arithmetic functions such as multipliers. When synthesizing for FPGAs, the logic portion of the design must be mapped to LUT (lookuptable) cells. The GateMate's Central Programming Element (CPE) does not consist of a conventional LUT, but a so-called LUT-tree. This enables logic functions with up to 8 inputs to be conveniently configured into a single CPE, without taking up large amounts of space. Since Berkeley ABC is usually used to map logic functions to N-input LUT cells, we developed a library with a description of all LUT-tree functions. In addition to logic synthesis, the built-in RAM cells can be used with the aid of memory inference where yosys finds out which storage type and which configuration can best be assigned. Even though the GateMate architecture does not include any dedicated DSP
slices, multipliers with arbitrary size can be efficiently implemented using several CPEs. A comprehensive DSP inference, technology mapping or cascading is not required, as multipliers of any size can be formed using the CPE architecture. In the synthesis, a primitive with a variable number of inputs and outputs is generated for each multiplier according to its size. In addition, the SerDes block or the PLL can be instantiated via blackbox primitives.After the synthesis, the netlists can be implemented using the Cologne Chip Place&Route software. With an extension in an Open Place&Route tool such as nextpnr2 it would be even possible to get a complete design flow using open source tools.