Lecture Description:

With the challenges of 5G Radio ahead, service providers aim to migrate to virtualized, open and
cloud-native Radio Access Network (RAN) solutions in order to limit vendor lock-in, decentralize
and reduce infrastructure costs. Consequently, top telecom operators have formed the ORAN
alliance. FPGA accelerators are poised to play a key role on ORAN deployments because of their
high processing capacity, programmability, I/O versatility and standardized compatibility with
COTS server hardware. Yet, the definition of the hardware/software platforms that ultimately
implement the ORAN specifications is still an active R&D area. The definition of the role of FPGAs
in these platforms requires answers to several questions: Which functions of the ORAN specification are suited for FPGA acceleration? What are the performance gains with respect to CPU-based implementations and how do FPGAs contrast with other hardware accelerators in this context? How can FPGA accelerators be operated efficiently in fully virtualized RAN environments?

In this presentation, we analyze all three questions above. We select a key (and cross-workgroup)
element of an ORAN deployment: The secure data transport to and from the Open Distributed
Units (O-DUs) and the Open Central Units (O-CUs), which introduces very high throughput requirements and hence significant compute effort. We analyze the suitability of FPGA accelerators and FPGA-based SmartNICs for this element and present a reference implementation. The performance and host offload potential are shown through measurements in comparison to software implementations. First results show a 10x improvement in communication bandwidth. We also discuss alternative hardware accelerator platforms with respect to performance and prospective infrastructure costs. Thirdly, we discuss a concept for the integration of the acceleration kernels into virtualization and orchestration frameworks.