Lecture Description:

Many industrial and automotive applications have similar challenges: work in a power-constrained environment and perform defined algorithms in an efficient way with limited staff with in-depth FPGA know-how. High Level Synthesis (HLS) is a path that has established itself over the last few years that allows the creation of FPGA designs based on high-level languages of C and C++. HLS is a very efficient way of designing with significantly reduced development time as it splits the development and verification of the required algorithms from the hardware synthesis. This presentation will show embedded software designers how they can utilize the techniques familiar to them for creation of hardware designs targeted for a low power FPGAs. The outcome is to have a single piece of IP for this defined algorithm that can be incorporated into a larger, potentially already existing design. The presentation will also briefly show where HLS is not suited, and where traditional FPGA techniques should be utilized. For an example of a well-defined algorithm, a Canny edge algorithm is used. This is initially simulated in C++ and afterwards targeted to Microchip’s MPF300 Video Kit. The targeting towards the hardware shows how to analyze the current size and performance of the chosen synthesis results for a design-space exploration. It also shows how to influence the final results using various optimization techniques with little to no modification of the original C code.