Lecture Description:

5G networks require greater performance and lower latency because of a multifold increase in connected devices and applications. This requirement demands improved channel quality and error correction schemes on 5G data transmission channels connecting massive MIMO 5G antennas to 5G base stations. 
5G transmission channels use low-density parity check (LDPC) codes for integrity of data transmission between radio and base stations. The LDPC encode and decode is a compute intensive operation which consumes multiple high-end CPU cores hence increasing the cost and power of the 5G base station. The performance of LDPC encode and decode operation depends on multiple parameters such as code block sizes, number of iterations and LLR bits etc. Though software allows for flexibility in configuration of these parameters, it still requires high-end commercial off-the-shelf servers with a large number of high-end CPU cores to be used at 5G base stations. This problem can be addressed by adding hardware acceleration into the mix which allows the same flexibility with higher performance and a smaller server footprint. By using programmable accelerators, many more 5G massive MIMO sectors of higher bandwidth can be aggregated at the base station as compared to software-only base station implementation for 5G layer-1 processing. 5G Massive MIMO based remote radio units (RRUs) connect with virtualized/containerized base stations through an efficient Ethernet based eCPRI interface with support for O-RAN framing. O-RAN based fronthaul also requires support for timing synchronization with reference clock as voice, and data applications running on 5G mobile devices. Since 5G architecture needs massive MIMO antennas, aggregated for multiple cells to connect with virtualized base stations at very high throughputs, the fronthaul interface required hardware support for O-RAN processing of high throughput eCPRI interface. Traditional solutions only process the known layer-2 and layer-3 fields and depend on software for O-RAN processing for I/Q data mapping to wireless L1 software but as the throughput increases as a result of multiple sector aggregation, the software cannot keep up with high throughput O-RAN processing even with multiple high performance CPU cores. In such scenarios, FPGA based fronthaul termination with timing support can be ideal implementation for 5G base stations.