Lecture Description:

To reuse existing RTL blocks within the Acceleration Flow of Vitis requires a certain defined set of
interfaces and respective descriptions of these to enable the Vitis compiler to bind these blocks
into the given platform. This presentation describes these interfaces, the packaging process and the
platform connectivitiy. We will demonstrate how the IP component description is extended to
account for these dependencies and produce a *.xo archive that is integrated into a Vitis build.