Lecture Description:

While choosing a single chip FPGA/converter solution may be the right option for a narrow range of applications, having a separate signal processor and converter still offers higher flexibility in terms of part selection, cost and channel count scaling for a wider range of applications. The JESD204 standard defines how to link these two parts starting from 2006, but as the converters bandwidth requirements increased over time the standard evolved as well having JESD204C released in the late of 2017. Regardless of the revision, linking the two parts presents an increased level of complexity due the use of high speed transceivers clock chips and converters. This presentation is going to give a walk-through over the revisions of the standard, present the 8b10b and the 64b66b/64b80b linecoding defined in the latest revision, and provide a solution for mitigating the integration effort associated with the complexity of such systems using the JESD204 Interface Framework offered by Analog Devices. The JESD204 Interface Framework is a system-level software and HDL package targeted at simplifying system development by providing a performance optimized IP framework that integrates complex hardware such as high speed converters, transceivers and clocks with various FPGA platforms.
The framework is cross vendor (Xilinx and Intel) compatible, and dual licensed with open source (released under GPL) or paid commercial license.