Description:

A design of the readout architecture for the ALICE 3 Time-of-Flight (TOF) detector, and the implementation of a FPGA based test bench to validate the system performance is described. 

ALICE 3 is the proposed next-generation upgrade of the ALICE (A Large Ion Collider Experiment) detector currently installed on the Large Hadron Collider (LHC) at CERN.[1] The ALICE experiment focuses on heavy-ion particle physics research. ALICE 3 will be a new detector, planned for installation during the Long Shutdown 4 (LS4) between 2034–2035.[2] The 

TOF readout system integrates CERN’s lpGBT, front-end control and data-aggregation ASIC, and VTRx+ optical transceiver, module. The test bench uses a FPGA based Pixel-sensor emulator to generate the detector data. The emulator, designed on an Intel Arria 10 GX FPGA transmits data 

via electrical lines at up to 320 Mb/s to the lpGBT. The data is aggregated and forwarded via optic fiber at up to 10.24 Gb/s to an AMD Kintex UltraScale+ KCU116 FPGA. The KCU116 board implements the lpGBT-FPGA decoding chain to emulate the processing done within the ALICE 

counting room. Firmware design aspects, including clock distribution and phase alignment, are discussed. Measurements of the quality of the distributed 40 MHz reference clock, showed a RMS jitter of 2.23ps, contributing <12% to the total time resolution of the sub-detector. Long-run link tests at 5.12 and 10.24 Gb/s show error-free operation over 4.7 hours with BER < 6.375×10-13, 95% C.I. The test bench provides a reliable platform for validating the characteristics and performance of the ALICE 3 TOF readout system and provides a foundation for future development.

Level: Intermediate

Description:

Time-to-Digital Converters (TDCs) are specialized electronic devices used to measure the time interval between events with high precision. TDCs are essential in applications requiring precise timing information, such as in high-energy physics experiments, medical imaging, and communication systems.

FPGAs have been used for implementing TDCs due to their ability to handle multiple timing channels simultaneously and achieve high resolution and accuracy thanks to their fine-grained timing capabilities and fast processing speeds.

For even higher resolutions, it is possible to use the GateMate FPGA's innovative carry and propagation lines (CP-lines), which form the arithmetic part of the so-called Cologne Programmable Elements (CPE). This advanced architecture achieves a remarkable and unprecedented resolution of just 5 picoseconds, making them ideal for applications requiring ultra-precise timing accuracy.

Level: Intermediate

Description:

The presentation first explains the fundamental testing approach for FPGA-based systems and then discusses how these fundamentals can be applied to automation, including the different approaches to implementation. It focuses on how to design robust test concepts that improve fault coverage, reduce test time, ensure reproducibility, and enable reliable verification in production environments.

Using real-world examples, the talk explains how test requirements can be derived from system architecture, how automation strategies can be implemented efficiently, and how common pitfalls in FPGA testing can be avoided.

In the second part, the presented methodology is applied to the prodesign RAVEN Lab Switch system as a concrete case study. This demonstrates how the theoretical concepts translate into practice, highlighting design decisions, automation approaches, and measurable benefits in terms of test time, reproducibility, efficiency and maintainability.

Level: Intermediate

Description:

Many embedded systems today are directly exposed to ever-growing threats, primarily due to the continued democratisation of attacker techniques and technologies. Even the strongest of the state-of-the-art security hardware offerings can suffer from exposure of sensitive security materials. When the concept of a ‘Root-of-Trust’ lies at the foundation of modern security architectures, losing our ‘Trust-in-the-Root’ becomes a potentially severe and unrecoverable problem, especially when embedded systems are highly distributed throughout our world. Attacks which are successfully carried out at this level provide system manufacturers/owners with two choices: reduce the operating capabilities of the product – trade-off device capability for peace of mind; or discard the device entirely – accepting the losses incurred. 

This session will cover the possibilities of how reimagining the security architecture with “Zero- Knowledge Initial Enrolment” in mind can enable the management, mitigation - and most critically - recovery of IoT devices from sophisticated attacks. As a result, manufacturers can lower the cost of logistics and key-handling/provisioning, support efforts to increase the difficulty of equipment overbuilding in an untrusted supply-chain and provide end-customers with ultimate control over device enrolment data (Zero Trust).

Level: Intermediate

Description:

FPGAs provide a flexible way to implement and modify packet processors which can be quickly adapted to new protocols and applications.  However, the development of these protocols requires skilled RTL engineers and takes time to implement and verify.

P4 is an open-source network domain-specific high-level programming language that provides a mechanism to implement packet processing pipelines.  It’s usable by both RTL and network engineers to implement novel packet processors in a fraction of the time compared with RTL.

This talk gives a brief overview of P4, its capabilities, and its scope and limitations, in the context of FPGA design.  This is followed by some examples of how P4 has been used in complete FPGA-based systems.  These range from traditional networking applications based around MPLS and flexible packet scheduling to more novel areas such as AI inferencing, Robotic control and TSN industrial applications.

Level: Beginner

Description:

In modern FPGA systems, it is sometimes not possible for engineers to fit their entire design into a single FPGA. In other cases, a system is deliberately split across two or more devices, such as an SoC and an FPGA. To control all parts of such designs, a bridge between these devices is required.

This talk discusses multiple approaches to inter-FPGA communication and provides an introduction to AMD’s AXI Chip2Chip IP core. It presents an overview of the C2C architecture, including channel multiplexing, deskew logic, link training, clocking, and interrupt forwarding. Attendees will learn key implementation guidelines.

The session will also demonstrate a practical design showing how to use AXI Chip2Chip in a multi-FPGA system.

Level: Intermediate

Description:

Discussing methodologies and tools for verifying and testing FPGA designs, ensuring reliability and correctness. Various verification strategies, including simulation-based verification, formal verification, and hardware emulation, highlighting their strengths and limitations. Provide insights into developing effective testbenches, including the use of self-checking testbenches, stimulus generation, and testbench automation.Present FPGA prototyping as a verification methodology, allowing the design to be tested in a more realistic environment before final implementation.Address strategies for regression testing and automation, ensuring that verification tests are continuously applied as the design evolves.Present common challenges faced in FPGA verification, such as handling complex designs, managing simulation time, and ensuring comprehensive coverage.

Level: Intermediate

Description:

The AMD RFSoC had a huge impact on the industries with its high-speed ADC and DAC combine in the same chip as an FPGA fabric with CPU compute power. While other vendors are adding similar architectures to their portfolio, the RFSoC had already a couple of revisions and is widely adopted.

In this talk I will show the architecture and features of the RFSoC as well as the new Versal RF. We will compare them to Altera's direct RF-Series FPGA and finally conclude how the general data flow and computing structures should look like.

Level: Beginner

Description:

A hardware root-of-trust (HW-RoT) is an essential component for establishing and maintaining digital trust on a computing platform. Solutions oXering a range of HW-RoT services for a host system include TPM (Trusted Platform Modules), DICE (Device Identification Composition Engine), and open source implementations such as OpenTitan and Caliptra. Verification and validation

of these may prove challenging, especially when applied in high-security assurance scenarios. In this presentation we establish a base for essential HW-RoT functions and requirements, and propose a foundation and

architecture for building an FPGA-based Root-of-Trust for enhanced security,

lower power consumption, etc.

Level: Intermediate

Description:

Efinix features an innovative architecture. This opens up new possibilities for you in terms of size and integration on your PCB, making it easier to design and more cost-effective in space-constrained environments.

Our System-in-Package (SiP) devices offer a compact, all-in-one solution that still provides enough space for a variety of interfaces to connect the essential components for your project. 

In this session, we will show you examples of what you can achieve with these small packages and SiP devices, and how you can benefit in terms of cost, performance, size, development speed, and more.

Level: Beginner

Description:

According to the 2024 Wilson Verification Survey 42% of FPGA projects are used in Safety Critical systems.  As a result, requirements tracking capabilities, such as those provided by Open Source VHDL Verification Methodology (OSVVM), are necessary to provide evidence that requirements are met.    

OSVVM’s view of requirements is that they are either a condition (pass/fail) or sets of independent conditions that need to be exercised and observed.  OSVVM uses affirmations (such as AffirmIf) to track conditions passing or failing.  OSVVM uses functional coverage to tracks sets of independent conditions.  Both of these capabilities support a count, a goal, and a failure count.  When a requirement needs to be observed more than once, tracking failures is important as any failure means the requirement fails.  Tracking requirements just adds additional reporting which is required for safety critical designs.    

As a result, tracking requirements is a core part of OSVVM’s capability. 

Level: Beginner

Description:

Next-generation wireless, satellite, and instrumentation systems demand multi-GHz instantaneous bandwidth with high signal quality and energy efficiency. Conventional wideband data converter architectures depend on oversampling and heavy digital filtering, resulting in high power consumption, excessive data rates, and reliance on deep-submicron CMOS nodes that are often unsuitable for analog and RF circuits.

This talk presents Fourier-Domain data converter architectures from INCIRT GmbH that enable multi-GHz bandwidth with significantly reduced power and increased data throughput, while interfacing efficiently with FPGAs and RF-SoCs. Performance scaling is independent of advanced digital CMOS, allowing integration in RF-capable processes. Silicon results and applications in mmWave, early-6G, satellite, and test systems are discussed.

Level: Intermediate

Description:

In FPGA design, correctly handling clock domain crossings, buffering data streams, and matching data widths is critical for reliable and maintainable systems. The Open Logic FPGA Standard Library (open source) provides building blocks for these challenges, but many users struggle to understand when and how to combine them effectively.

This talk will walk you through the CDCs, FIFOs, and width converters in Open Logic and provide clear guidance on selecting and composing them for different scenarios, including asymmetric buffering and varying bandwidth requirements. Attendees will leave with actionable rules and patterns to use Open Logic building blocks correctly, avoid common pitfalls, and simplify FPGA system design.

Level: Intermediate

Description:

The EU Cyber Resilience Act (CRA) and Radio Equipment Directive (RED) are driving new requirements for crypto agility, lifecycle trust, and veritable resilience in industrial and embedded systems. As post-quantum cryptography (PQC) adoption accelerates, manufacturers must integrate solutions that can evolve with algorithms while maintaining compliance and operational uptime.

This session introduces a united FPGA-TPM architecture that combines SealSQ’s PQC-enabled TPM with FPGA-based adaptability to deliver both a trusted root of resilience and crypto updatability at the edge.

We will show how the integrated approach:

• Uses the TPM as a standards-compliant trust anchor for secure boot, attestation, key management, and post-compromise recovery.
• Leverages fast FPGA fabric to accelerate PQC algorithms and enable real-time cyber resilience mitigations such as anomaly altering, rollback protection, and runtime policy enforcement.
• Provides dual assurance: TPM-anchored identity and policy enforcement plus FPGA-based crypto and resilience agility as standards and threats evolve.
• Simplices compliance with IEC 62443, ETSI, RED, and CRA by unifying wireless security, cyber resilience, and lifecycle-updatable cryptography.

Attendees will learn how this combined TPM-FPGA strategy delivers veritable trust, PQC readiness, and regulatory compliance—ensuring industrial edge devices remain secure and resilient against both current and quantum-enabled threats.

Level: Intermediate

Description:

Effective clock and reset management is essential for reliable RTL development in FPGA designs. 

A simple synchronous clocking concept with a limited number of global clocks is key in early design stages. 

Modern FPGAs offer extensive clocking resources that allow the clock architecture to be adapted to performance, 

timing closure, and I/O synchronization requirements. Synchronous resets must be adjusted accordingly when clock domains change. 

A centralized and well-structured clock and reset system simplifies these adaptations and reduces development effort and time.

Level: Beginner

Description:

The European Union’s evolving cybersecurity landscape—anchored by the Radio Equipment Directive (RED) and the forthcoming Cyber Resilience Act (CRA)—demands robust, hardware-level security mechanisms for connected devices. 

This paper presents the integration of SIPHash IP, a lightweight cryptographic Message Authentication Code (MAC), as a foundational component for achieving RED compliance and CRA readiness.

We demonstrate how SIPHash IP supports RED’s mandatory requirements for data integrity, fraud prevention, and secure firmware validation, particularly under Articles 3.3 (d), (e), and (f). 

Furthermore, we explore its role in CRA-aligned security architectures, including secure boot flows, SBOM documentation, and lifecycle vulnerability management. 

With a minimal resource footprint and high throughput, SIPHash IP is well-suited for constrained environments such as smart AR/VR systems, industrial IoT, and automotive platforms.

We use Smart AR/VR case study to illustrate how SIPHash IP enhances trust in vision sensor data and firmware updates. 

The paper concludes with a roadmap for integrating SIPHash into RED/CRA compliance workflows, aligning with EN 303 645 (security for consumer IoT)  and EN 18031(security for radio equipment- within scope of RED) standards.

Level: Intermediate

Description:

Where SystemVerilog builds verification capability directly into the language, OSVVM uses data structures to implement verification capability such as Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging, and message filtering (logs).    

These data structures are implemented using a singleton structure created in a package.  Unlike protected type based implementations, singletons allow us to create a use model that is as simple as build in language features.   

This presentation provides an in-depth exploration of the usage of these data structures plus some new ones that are currently being developed.

Level: Beginner

Description:

Effective thermal management is a key aspect of reliable FPGA system design. This presentation demonstrates how thermal behavior can be analyzed and optimized when using Efinix FPGAs. Thermal images from real-world designs are presented to illustrate typical heat distribution and operating conditions. The advantages of reduced power consumption are discussed, including the ability to design smaller PCBs with less emphasis on thermal spreading and the elimination of active cooling such as fans. 

The available Efinix power estimation tools, are introduced as a practical method for early thermal planning. Finally, the presentation addresses the risk of thermal runaway and emphasizes the importance of continuous temperature monitoring using temperature sensors to ensure safe and reliable operation under all conditions.

Level: Intermediate

Description:

At DESY, the increasing complexity of control systems for particle accelerators requires a standardized approach to FPGA development. We present fwk, an open-source framework designed to abstract design logic from underlying vendor-specific implementation tools. The framework provides a unified environment for managing IP cores, project generation, and register mapping across different hardware platforms. Complementing this infrastructure, DESY is actively releasing a growing library of VHDL IP cores to the public, underscoring an institutional commitment to open-source instrumentation. Additionally, fwk addresses the integration of heterogeneous processing units by coordinating the build processes for embedded runtime environments, such as Yocto and FreeRTOS. The presentation outlines the framework’s design principles and provides an overview of its application in current accelerator subsystems.

Level: Intermediate

Description:

As edge computing grows, security becomes a fundamental requirement for FPGA-based systems. This presentation examines strategies for securing FPGA designs against threats such as IP theft, tampering, and data breaches. Topics include hardware root of trust, secure boot, encryption of bitstreams, and lifecycle management. We will highlight how non-volatile FPGA architectures and integrated security features provide robust protection without sacrificing performance. Participants will gain practical insights into designing secure, resilient FPGA systems for critical applications.

Level: Intermediate

Description:

FPGAs have long moved beyond programmable logic, evolving into platforms where adaptable hardware integrates with purpose-built engines to capture, move, secure, and interpret data. This keynote examines how the latest advancements scale these capabilities across cost-optimized to high-end architectures—integrating dense signal processing, next-generation RF, hard security, and AI acceleration to enable physical AI, where intelligence directly senses and acts in the real world. We will also explore AI-powered FPGA workflows to simplify design closure.

Description:

Efinix devices integrate high-speed SerDes and hardened LPDDR4 IP, making them well suited for video applications that require real-time processing, such as pixel-level ISP or video-overlay designs. This presentation starts by examining the interfacing of video sources and sinks, followed by a discussion of internal design strategies for achieving low-latency datapaths. It demonstrates how the SerDes can be operated in ultra-low-latency modes and explores the LPDDR4 controller architecture to show how sub-frame latency can be achieved, even for processing that depends on frame history. The presented design is concluded with a live demonstration. Attendees will gain practical insight into designing and debugging low-latency video datapaths on Efinix devices and learn how to avoid common architectural pitfalls.

Level: Intermediate

Description:

UVVM is currently being used by 27% of all FPGA designers and 25% of all ASIC designers worldwide - and increasing. This is due to the improvement UVVM yields in both FPGA quality and development time. This open source Library and Methodology has the most extensive VHDL verification support available and lets you verify complex DUTs in a very efficient manner, providing overview, readability, modularity, reusability, and debuggability similar to UVM, but far simpler to use.

UVVM has been significantly updated through several ESA (European Space Agency) UVVM extension projects over the last few years, and we are currently working on even more new features - in tight cooperation with ESA.

UVVM provides a testbench kick start with open source BFMs and verification components for UART, SPI, AXI, AXI-lite, APB, AXI stream, Avalon MM + Stream, I2C, GPIO, SBI, GMII, RGMII, Ethernet, Wishbone, Clock generator, and Error injector. You also have all the other functionality you need for your testbench, like Requirements Tracking, Enhanced Randomisation, Functional Coverage, Scoreboards, Error Injection, etc.

And if you have a really simple DUT, then you just use the basic parts of UVVM.

This presentation will give you a brief introduction to UVVM - but also show the most important features and explain how they will help you make a better testbench and develop this much faster.

Level: Beginner

Description:

The European Union's MiFID II (Markets in Financial Instruments Directive II) framework, specifically RTS 6 (Regulatory Technical Standards 6), mandates rigorous pre-trade risk controls for High-Frequency Trading (HFT) and algorithmic firms to prevent contribution to disorderly market conditions. Historical market failures, ranging from the 2010 Flash Crash and the 2012 Knight Capital outage to the recent 2022 Nordic disruption, underscore the catastrophic consequences of inadequate risk enforcement. However, implementing comprehensive safeguards such as real-time price monitoring and position tracking purely in software often imposes latency penalties that compromise competitive execution.

This paper presents NanoShield, a software-managed, hardware-enforced Pre-Trade Risk Management (PTRM) platform. While the current deployment targets Nasdaq financial protocols to align with Borsa Istanbul’s infrastructure, the core engine is built around a protocol-agnostic intermediate representation. This abstraction enables straightforward adaptation to other exchange protocols with minimal changes to the enforcement logic. The complete network stack (including TCP) and the order-entry logic are implemented in hardware. In the FPGA data plane, orders are blocked or forwarded in-line based on a critical subset of RTS~6 controls, including static/dynamic price collars, real-time position limits, hierarchical scoping, and a hardware-actuated TCP flow kill switch. The resulting wire-to-wire latency is deterministic at approximately 390~ns (measured from start-of-packet), with a variance of $\pm$40~ns depending on the enabled risk rules.

Complementing the hardware, the software subsystem manages configuration and User Interfaces (UI) while constructing the Limit Order Book (LOB). Furthermore, the software performs a comprehensive shadow evaluation of all hardware-level controls, providing a redundant verification layer that ensures the integrity of the FPGA's decision-making process. By combining software-managed policy control, hardware-enforced determinism, and redundant multi-path risk evaluation, NanoShield delivers a resilient, regulation-compliant foundation for ultra-low latency algorithmic trading.

Level: Intermediate

Description:

Security in modern embedded systems begins at the hardware level. This session provides a comprehensive introduction to FPGA and Systems security, focusing on the internal architecture and the fundamental mechanisms that establish a "Root of Trust." 

We will explore how a device identifies itself and ensures integrity before executing a single line of logic. The lecture will break down the internal structures of the FPGA fabric and dedicated security blocks. 

We will cover the core principles of device authentication, the secure boot process, and how hardware-rooted identity prevents cloning and tampering. 

The target audience includes Hardware Designers, Embedded Systems Engineers, and Security Enthusiasts seeking a solid introduction to hardware-level security. It is tailored for those who want to understand the internal architecture of FPGAs, how silicon-based identities like PUFs are formed, and the fundamental processes of device authentication. The session is ideal for anyone looking to build a "Root of Trust" from the ground up.

The main theme of the presentation is establishing hardware-level trust through internal FPGA architecture and silicon-based identity. It focuses on how fundamental structures like PUFs create a unique, unforgeable identity to secure the device from the moment of power-on.

Level: Beginner

Description:

OSVVM comes with a powerful TCL scripting environment (OSVVM-Scripts), but not everyone likes TCL scripting, especially when it comes to project specific extension. On the other hand, some engineers use VUnit as a test runner, because scripting is done in Python. Let's bridge that gap and run OSVVM simulations from Python without TCL scripting knowledge.

This presentation will introduce EDA² (Electronic Design Automation Abstraction) and it's layer stack. It will show how to use EDA² layers e.g. how to read Vivado or OSVVM project files. The extracted configuration will be used to run an OSVVM simulation purely from Python. After simulation, various report formats will be created. Moreover, reports will be integrated into a Sphinx-based documentation, thus documentation and verification report can become one.

Level: Intermediate

Description:

Every ISP application is unique - and no IP core can hope to meet all possible requirements at the same time. Mini-ISP offers maximum flexibility by providing all Verilog sources under a permissive open-source license. This talk introduces Mini-ISP and the philosophy and design choices behind it. Mini-ISP building blocks are explained, with a focus on RTL implementation tricks.

Level: Intermediate

Description:

Assertions can be very useful in detecting problems in your design – and maybe even more important – detecting problems early where the problem arises. Assertions could be used in your design, typically to check assumptions, integration, relations, etc, but also in your testbench, typically to verify specific temporal properties. 

This presentation will show the use of simple VHDL-based assertions for static and dynamic properties for both design and verification. There will be examples using pure, verification platform independent VHDL assertions and the new assertion library in UVVM. 

The newest features in UVVM will also be shown and explained.

Level: Intermediate

Description:

AMD Spartan UltraScale+ is the new small, low-cost FPGA family that can provide extensive real-time capabilities in industrial environments. These industrial systems often consist of an extensive network of sensors and actuators that are to be connected to small real-time capable function nodes. In addition to sensors for environmental conditions, the sensors can also include, for example, video sensors of various wavelengths. 

In addition to data preprocessing and security functions, more complex evaluation processes are usually outsourced to higher levels or cloud-based systems. Fast, and in some cases extremely interference-resistant, connections to these systems must be in place. Based on these requirements, the Spartan UltraScale+ can be used to build a small functional node with USB 3, MIPI, and well over 100 freely configurable IOs up to 200 MHz in a very small space.

This presentation will show this setup and various applications. The possible variations in hardware design and programming will also be presented

Level: Intermediate

Description:

All modern cryptographic algorithms, whether they are implemented by hardware or by software, are all based on the digital  computations that are performed on physical devices.

When executing the cryptographic computations, the device consumes power and emits heat, electromagnetic radiation, and so on.

Fault injection involves manipulating environmental variables in a system (e.g. clock, power, temperature, etc.) in order to cause a fault – a disturbance in the normal operation of the chip.

As execution continues, the disturbance propagates, which results in undesired state.

Many FPGAs are vulnerable to such attacks.

In this talk we are going to understand how these attacks work and what are the Hardware and software mitigations.

Altera Agilex 5 and AMD Versal will be used as a use case.

Level: Beginner

Description to follow shortly

Description:

This presentation covers the transfer of data between FPGA and PC via Ethernet. Vendor-independent components are introduced, which establish direct hardware connections between AXI streams and UDP/IP/Ethernet packets.

Ethernet packets received by the PHY are packed directly into AXI stream packets. This stream is transferred to the system clock domain. The packets from a selected UDP port are filtered and its data is provided directly as an AXI stream. The remaining packets can be further filtered, routed to a processor, or simply discarded.

On the transmission side, the data of an AXI stream is divided into packets. Each packet is provided with a prestored UDP header, whose checksum is adapted to the current data by hardware. These packets are multiplexed with other packets, CRC data is added, and they are transferred to the clock domain of the PHY interface. There, they are finally output as Ethernet packets.

Level: Intermediate

Description:

Hardware Description Language (HDL) simulation is a critical step in digital design verification, but its computational demands often lead to lengthy simulation times, especially for large designs. This presentation explores how AMD Alveo acceleration cards, combined with open source frameworks and simulators, can significantly accelerate HDL simulation workflows. It discusses the integration of FPGA-based acceleration with open source tools, highlighting performance gains, practical implementation challenges, and additional benefits.

Level: Intermediate

Description:

In many cases, the limited availability of transceivers necessitates upgrading to a larger FPGA with additional transceiver capacity. However, there is now a solution that optimizes transceiver resource utilization within Agilex 3 and Agilex 5 devices. The GTS Dual Simplex mode enables support for multiple protocols on a single transceiver channel, providing enhanced flexibility and efficiency.

Level: Intermediate

Description:

Production facilities today are more and more required to be integrated into Ethernet networks. However, a significant amount of that equipment is "old" and hence vulnerable from a modern security perspective. At the same time, upgrading these machines to up-to-date security is often not possible due to lack of software support and risk. In addition, the EU strongly recommends higher levels of  traffic-data protection, which typically means encryption. How can the gap of requiring modern security on legacy hardware be bridged? This session will show a novel approach for plug-and-play inline AES encryption using FPGA-based SFP modules.

Hardware Developers and System Architects tasked with enabling modern security on legacy systems.

Legacy systems need to be protected on modern standards but often cannot be changed. With the right technology a security shield can be added on the communication paths which bridges this gap.

Level: Intermediate

Description:

With the implementation date of the EU Cyber Resilience Act (CRA) rapidly approaching, organizations developing digital products must ensure a thorough and practical understanding of secure-by-design principles. Central to CRA compliance is a robust cybersecurity risk assessment, encompassing asset identification, threat analysis, and the selection of effective security controls.

This presentation provides an overview of the key CRA requirements and outlines the concrete steps FPGA integrators should take to help secure their designs. Topics include establishing a secure development lifecycle, performing risk assessments and threat modeling, and selecting appropriate device features to help meet security objectives. The session will also examine AMD FPGA security capabilities and demonstrate how these features can be leveraged to help address certain concerns identified during customer risk assessment. 

Level: Intermediate

Description:

This work presents a novel methodology for improving the performance and efficiency of deep learning accelerator systems, particularly those utilizing colour filter array (CFA) imagers.

Traditional AI pipelines convert raw CFA sensor data into RGB images via demosaicing, which introduces artificial data, increases memory bandwidth requirements, and adds computational overhead throughout the neural network.

The proposed approach eliminates the demosaicing step by bypassing an image signal processing chain (ISP) and directly reordering the raw colour filter array (CFA) data into multiple channels, which are then fed into the deep learning model.

The approach can improve the inference processing by up to 4X and reduce training time by up to 4X.

Level: Advanced

Description:

High-assurance systems increasingly depend on FPGA devices whose deployed behavior is defined by the configuration bitstream, yet current verification flows stop at the HDL or routed-netlist level. This leaves a critical assurance gap because the bitstream itself is not verified. Bitstream Equivalence Checking (BEC) addresses this gap by proving logical and physical equivalence between the routed netlist and the configuration bitstream. Enverite® PV-Bit® is a vendor-approved BEC tool that performs this comparison without exposing proprietary bitstream formats or embedded IP. This presentation describes the application of BEC to four key assurance needs: extending verification evidence into the deployed bitstream, detecting unintended or malicious modifications, verifying preservation of modular isolation guarantees, and enabling delta verification for ECOs. The presentation emphasizes modular isolation, a recently introduced application area.

Level: Intermediate

Description:

Throughout the whole product development lifecycle there is more pressure than ever to move fast and do it right first time. With new PCB technologies such as High Density Interconnect, blind vias and embedded components becoming increasingly common we will discuss test methodologies and architectures at both device and board level which can help engineers make the right choice for their needs. There is no golden ticket!

Level: Intermediate

Description:

This presentation explores FPGA design strategies for aerospace applications using low-power Lattice FPGA platforms. Key topics include Radiation mitigation techniques such as Triple Modular Redundancy (TMR) and memory protection, configuration integrity and secure boot implementation, and deterministic startup architectures suitable for mission-critical control systems. 

The session also compares flash-based and SRAM-based FPGA technologies in the context of single-event upset (SEU) resilience, power budgeting, and field update capability.

Level: Intermediate

Description:

With over two decades of experience in consulting companies on FPGA design all over Europe and having taught VHDL-based FPGA and ASIC design to more than 1,000 students, the author continues to encounter recurring challenges in FPGA design. This talk is Vol. 2 of the Don’t! collection of last year and again aims to highlight some quite basic, but still common pitfalls and misconceptions in FPGA design, including, but not limited to:

• Is static Timing Analysis essential, optional, or automatic? Subtitle: Have you ever written an .sdc (or .xdc) file?
• The clock is running too fast. What to do? Strobe signals, gated clocks, or generating a slower clock from the faster one?
• The clock is just a signal, isn’t it? That comes in handy! Let us just use it that way aside of its clock role…    Ups!
• “VHDL provides the function rising_edge() to detect rising edges in the design.” Why should I spare it for clock signals only?
• Synchronizing needs at least a single flip-flop. Right or wrong?

Level: Beginner

Description:

Embedded AI technologies are advancing rapidly in FPGAs and are increasingly used to enhance performance, functionality, and safety across industries. As AI becomes integrated into higher-risk applications, failures can lead to serious consequences such as reputational damage, infrastructure disruption, financial loss, or harm to people and the environment. 

Systems with significant risk potential may be classified as high-risk under the EU AI Act, which requires documented accuracy levels and appropriate performance standards. Beyond regulatory requirements, accuracy is also crucial for functional safety because AI systems involve probabilistic behavior and variability rather than deterministic outcomes. 

This talk presents a framework for identifying AI-related risks and determining both the required and achievable reliability and accuracy of AI systems. It also gives a status on ISO/IEC 22440 - Artificial intelligence — Functional safety and AI Systems, currently in development.

Level: Beginner