Agenda - 8 July 2021
08:40 - 08:55 am
Opening Session Organizers - ELEKTRONIKPRAXIS & PLC2
09:00 - 09:40 am
System Generator for DSP: Super Sample Rate Overview (45 min)
Level: Intermediate
Speaker: Ernst Wehlage | PLC2 GmbH (view description)
09:45 - 10:25 am
Model-Based FPGA, ASIC and SoC Design in the Context of Functional Safety (45 min)
Level: Beginner
Speaker: Baruch Mitsengendler | The MathWorks GmbH (view description)
10:30 - 11:00 am
Break-Out with Partners
11:00 - 11:40 am
From "Pair Programming" to "Collaborative Editing" (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Martin Weitzel | Ingenieurbüro Martin Weitzel (view description)
11:45 am - 12:25 pm
Putting EDA Tools into Containers for CI (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Patrick Lehmann | PLC2 GmbH (view description)
12:30 - 12:45 pm
Break
12:45 - 01:30 pm
Drawing and winner announcement of the 10 Xilinx AI-Starter-Kits
01:30 - 02:00 pm
KEYNOTE: The future of high level design (30 min)
Speaker: Luis Murillo | Silexica (view description)
02:00 - 02:40 pm
Build production ready Vision solutions with the Xilinx K26 SOM and the AppStore (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Jens Stapelfeldt | Xilinx (view description)
02:45 -03:25 pm
A fully-integrated Xilinx MPSOC based drone/robotics platform (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Dirk van den Heuvel | TOPIC Embedded Systems (view description)
03:30 - 04:00 pm
Break-Out with Partners
04:00 - 04:40 pm
ROS-Integration (45 min)
Level: Beginner/Intermediate
Speaker: Sören Heß | PLC2 Design GmbH (view description)
04:45 - 05:25 pm
Breaking the TOPS ceiling with sparse neural network (45 min)
Level: Intermediate
Speaker: Nick Ni | Xilinx (view description)
Speaker: Lawrence Spracklen | Numenta
05:30 pm
Closing Session - Day 3
08:40 - 08:55 am
Opening Session Organizers - ELEKTRONIKPRAXIS & PLC2
09:00 - 09:40 am
From Sensor to Image with the Crosslink NX (45 min)
Level: Beginner
Speaker: Thorsten Heimann | Helion GmbH (view description)
09:45 - 10:25 am
Building a small footprint FPGA based low-power PCIe-system for sensor bridging applications (45 min)
Level: Beginner/Intermediate
Speaker: Martin Kellermann (view description) & Deepali Gupta | Microchip Technology GmbH (view description)
10:30 - 11:00 am
Break-Out with Partners
11:00 - 11:40 am
Bringing 3D data to deep learning (45 min)
Level: Intermediate
Speaker: Andy Luo | Xilinx (view description)
11:45 am - 12:25 pm
Accelerating face applications with Vitis-AI (45 min)
Level: Beginner
Speaker: Mario Bergeron | Avnet (view description)
12:30 - 12:45 pm
Break
12:45 - 01:30 pm
Drawing and winner announcement of the 10 Xilinx AI-Starter-Kits
01:30 - 02:00 pm
KEYNOTE: The future of high level design (30 min)
Speaker: Luis Murillo | Silexica (view description)
02:00 - 02:40 pm
Small-footprint machine learning inference for the intelligent edge (45 min)
Level: Beginner
Speaker: Altaf Khan | Infxl (view description) & Martin Kellermann | Microchip Technology GmbH
02:45 - 03:25 pm
Real-time capable and low-power systems for Vision and AI - why architecture matters (45 min)
Level: Beginner
Speaker: Sören Heß | PLC2 Design GmbH (view description)
03:30 - 04:00 pm
Break-Out with Partners
04:00 - 04:40 pm
Energy Efficient Extendable Artificial Intelligence Acceleration with FPGA (45 min)
Level: Beginner/Intermediate
Speaker: Michael Breiter | EYYES GmbH (view description)
04:45 - 05:25 pm
Implementing a low-power Machine Learning application for Smart Embedded Vision (45 min)
Level: Beginner/Intermediate
Speaker: Christian Rudel | Microchip Technology GmbH (view description)
05:30 pm
Closing Session - Day 3
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