Lecture Description:

Most high-performance DSP applications today need to deal with very high-speed data. Modern ADCs are capable of sampling signals at sample rates up to several giga-samples per second. Programmable Logic and FPGA devices can support that highest throughput rate only when using data parallelism. Xilinx Super-Sample Rate (SSR) is a toolbox and IP collection to define the i/o interface solution where a DSP algorithm like FIR and FFT can easily be build using data parallelism. In this session you will get the technical understanding of Xilinx SSR when using Matlab Simulink with the Xilinx System Generator tool for the hardware architecture development.