Lecture Description:

PCIe is a well-established standard, typically with pre-defined form factors. However, it is also used in embedded systems with tight constraints on power and physical size. In these embedded systems the implementation of PCIe hardware must be very effective and should use little to no FPGA resources. Additionally, small device packages are required that allow the use of cost-effective PCB technology. This session will demonstrate how to create a Gen2x4 PCIe system for a bridging application with two different sensors (imager and LIDAR) into a low-power FPGA. It will also demonstrate how the special package layout of this FPGA can be utilized for saving cost during manufacturing of the PCB. Estimations of the small power consumption for the FPGA, based on the implemented design, will be shown. The PolarFire® FPGA used for this session is available in an 11x11 mm² package with 0.5 mm pitch. This pitch is typically considered as expensive to manufacture. Several techniques will be shown that are reducing manufacturing cost and allow the use of layout rules of the well-established and cost-effective 0.8 mm board pitch.