Lecture Description:

Using Machine Learning (ML) algorithms is moving strongly into edge devices which often are constrained by physical size and power budget. Additionally, ML experts often are used to work on languages like Python and appropriate frameworks as Caffe, Tensorflow, PyTorch or others which are very different from the usual tools and languages used by embedded designers.
This session will talk about the available and required software and hardware components for implementing a trained network for a smart embedded vision application on a low-power Field Programmable Gate Array (FPGA). The required steps will be shown to take that trained network from one of the ML frameworks and port it onto an FPGA. This porting involves model optimization, quantization from typical floating point values into 8-bit integers, calibration to 8-bit representation plus the creation of the final runtime generation.
Several important features of the used VectorBlox™ accelerator development kit include:
-   No FPGA-experience is needed for targeting the trained network for the FPGA-IP
-   Early estimation of the ML-performance is possible using a capable simulator; hence no time-consuming implementation is required for initial performance-estimations.
-   The IP where the ML inference is run is available in different performance classes, even very small FPGAs.
-   The VectorBlox IP can run on a pure FPGA and does not require any hardened application processor. Embedded devices with hardened Processing Systems are supported too.
An easy to demonstrate use-case with cameras will be used, however some other potential use-cases will be shown.