Agenda - 6 July 2021
08:40 - 08:55 am
Opening Session with the organizers - ELEKTRONIKPRAXIS & PLC2
09:00 - 09:40 am
Modern VHDL testbenches – An AXI-stream example, first dead simple, then advanced. (45 min)
Level: Intermediate/Expert
Speaker: Espen Tallaksen | EmLogic AS (view description)
09:45 - 10:25 am
OSVVM: The New Stuff (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Jim Lewis | SynthWorks Design Inc. (view description)
10:30 - 11:00 am
Break-Out with Partners
11:00 - 11:40 am
Using OSVVM’s AXI Model to Verify a Complex Video Processing System (45 min)
Level: Intermediate & Expert
Speaker: Patrick Lehmann | PLC2 GmbH (view description)
11:45 am - 12:25 pm
Editing HDL code in 2021: are we ready for the cloud yet? (45 min)
Level: Beginner
Speaker: Sergei Zaychenko | Sigasi nv (view description)
12:30 - 12:45 pm
Break
12:45 - 01:30 pm
COUCH TALK: Chip shortage: How to locally handle the global issue.
Could increased local IC-production capacity be a solution for the future?
Participants:
Johann Wiesböck | Editor in Chief, ELEKTRONIKPRAXIS (Moderator)
Guido Überreiter | VP Tapeout, Mask and Postfab Operations, GLOBALFOUNDRIES
Hermann W. Reiter | Managing Director, Digi-Key
Alfred Birgmann | Vice President Global Procurement (GP), Zollner Elektronik AG
Prof. Dr. Robert Weigel | Department of Electrical-Electronic-Communication Engineering, FAU
01:30 - 02:00 pm
KEYNOTE: On how FPGA developers can build & deploy disruptive AI products (30 min)
Speaker: Ramine Roane | Xilinx (view description)
02:00 - 02:40 pm
Secure Platform – Digital Sovereignty as motivation for a secure, sustainable, and open IT ecosystem in Europe (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Dr. André Kudra | esatus AG (view description)
02:45 - 03:25
Cyber Resiliency is becoming critical for all Embedded Systems (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Eric Sivertson | Lattice Semiconductor Corporation (view description)
03:30 - 04:00 pm
Break-Out with Partners
04:00 - 04:40 pm
How to Accelerate a Post-Quantum Cryptographic Algorithm using FPGAs (45 min)
Level: Intermediate
Speaker: Nicholas Moellers | Silexica GmbH (view description)
04:45 - 05:25 pm
Multi-Protocol Encoder-Interface IP for Safety Encoder (45 min)
Level: Beginner/Intermediate
Speaker: Jens Onno Krah | TH Köln (view description)
05:30 pm
Closing Session - Day1
08:40 - 08:55 am
Opening Session with the organizers - ELEKTRONIKPRAXIS & PLC2
09:00 - 09:40 am
Lattice CrossLink-NX FPGAs (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Eugen Krassin | Krassin Consulting GmbH (view description)
09:45 - 10:25 am
ECP5 SERDES deep dive (45 min)
Level: Beginner/Intermediate/Expert
Speaker: David Kirchner | Krassin Consulting GmbH (view description)
10:30 - 11:00 am
Break-Out with Partners
11:00 - 11:40 am
FPGA new Quantum Architecture (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Harald Werner | Efinix Inc. GmbH (view description)
11:45 am - 12:25 pm
PolarFire SoC - Lowest Power, Multi-Core RISC-V SoC FPGA (45 min)
Level: Beginner
Speaker: Saad Riaz Qazi | EBV Elektronik GmbH & Co. KG (view description)
12:30 - 12:45 pm
Break
12:45 - 01:30 pm
COUCH TALK: Chip shortage: How to locally handle the global issue.
Could increased local IC-production capacity be a solution for the future?
Participants:
Johann Wiesböck | Editor in Chief, ELEKTRONIKPRAXIS (Moderator)
Guido Überreiter | VP Tapeout, Mask and Postfab Operations | GLOBALFOUNDRIES
Hermann W. Reiter | Managing Director, Digi-Key
Alfred Birgmann | Vice President Global Procurement (GP), Zollner Elektronik AG
Prof. Dr. Robert Weigel | Department of Electrical-Electronic-Communication Engineering, FAU
01:30 - 02:00 pm
KEYNOTE: On how FPGA developers can build & deploy disruptive AI products (30 min)
Speaker: Ramine Roane | XILINX (view description)
02:00 - 02:40 pm
Your product is broken, and you don't know - An uncomfortable truth (45 min)
Level: Beginner
Speaker: Michael Tretter | Pengutronix e.K (view description)
02:45 -03:25 pm
How to take full advantage of Intel’s Platform Designer (formerly Qsys) (45 min)
Level: Intermediate
Speaker: Wolfgang Loewer | El Camino GmbH (view description)
03:30 - 04:00 pm
Break-Out with Partners
04:00 - 04:40 pm
IP core development of phase-shift calculation for 3D cameras (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Dr. Jörg Pospiech | AVT GmbH (view description)
04:45 - 05:25 pm
Correlation between bitstream and real implementation (Zynq UltraScale+ MPSoC-FPGA (45 min)
Level: Beginner/Intermediate/Expert
Speaker: Thomas Kuhn | HTV Halbleiter-Test & Vertriebs GmbH (view description)
05:30pm
Closing Session - Day 1
An event by brands and partners of
Copyright © 2024 Vogel Communications Group
This website is a trademark of Vogel Communications Group. An overview of all products and services can be found at www.vogel.de