Lecture Description:

FPGAs are well suited for massive parallel video processing. The sweet spot of maintainability, controllability and testability as well as implementation time, FPGA resource utilization and timing closure can be achieve with a design written mainly in VHDL. In addition some third-party, vendor and open source IP cores are used. Many systems architects and project managers might fear such a “low-level” approach, because verification by simulation looks complicated and challenging.
 
In this talk, I’ll present a system architecture breakdown of a generalized complex video processing system that utilizes VHDL to the maximum supported level by vendor tools (e.g. Xilinx Vivado). I’ll showcase how good hierarchical design leads to fast progress, easy maintenance and good testability. All components and the whole
processing pipeline will be verified using OSVVM’s latest AXI models (AXI4, AXI4-Lite, and AXI-Stream).