Lecture Description:

Do you want to see how easy you can very your FPGA or ASIC? Join in to see this exemplified with a testbench for an AXI-stream based data flow design – using UVVM, the world’s #1 VHDL verification
methodology. Most testbenches verifying a complex DUT are relatively unstructured and difficult to understand, modify, extend, maintain and reuse. You can often easily reduce the verification time by at least a factor of two by having a well structured and easy to understand test harness, and writing commands at a higher abstraction level – allowing a good and complete testcase overview by just looking at a simple test sequencer with easy to understand high level commands. This presentation will show first how interface handling procedures (BFMs) can be applied in a very simple way to verify a DUT. Then we will show how a more advanced testbench using verification components, model, scoreboards and high-level transactions will allow more thorough verification of more complex DUT scenarios in a very structured and simple way. UVVM has exploded over the last few years and is now the world’s number 1 VHDL verification methodology.