Lecture Description:

The Platform Designer (formerly Qsys) is part of the Intel® Quartus® Prime software and freely available in all editions of the tool. It saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. You can integrate optimized and verified Intel FPGA IP cores into a design to
shorten design cycles and maximize performance. Platform Designer also supports integration of IP cores from third-parties, or custom components that you define. This presentation highlights some unique, yet very powerful features like:
- Fast Timing Closure through Pipelining and insertion of Bridges
- Debugging with System Console
- Automatic Testbench Generation
- Integration of custom logic with readymade IP components from the library

The hierarchical and structured flow enables scalable designs, team-based design, and maximizes design reuse. The Avalon interface family defines interfaces appropriate for streaming high-speed data, reading and writing registers and memory, and controlling off-chip devices.
Components available in Platform Designer incorporate these standard interfaces.
Additionally, you can incorporate Avalon interfaces in custom components, enhancing the interoperability of designs. All this together reduces the design of complex systems to a lego-like integration of standard and custom components. When used together with outsourcing all or parts of the design the result will automatically be well documented, easy to understand and easy to maintain or extend.