Lecture Description:

Lattice ECP5 FPGA family has a high performance Serializer/Deserializer combined with low power and general purpose FPGA structure. This presentation gives the user a deep dive into this functionality. After an short ECP5 introduction the user get a detailed description of all SERDES function and of the implemented PCS (Physical Coding Sublayer). SERDES and PCS can be combined to support a high range of popular serial protocols.