Gabriel Chidolue

Siemens EDA

Gabriel Chidolue is a Product Engineering Manager in the Design Verification Technology group within Siemens EDA, a part of Siemens DI SW. 
He has over 20 years’ experience in Digital design (ASIC and FPGA) and verification. 
He started his career as a Hardware Design and Verification Engineer. He later transitioned into the EDA where he worked on 
FPGA Synthesis, Logic equivalency checkers and Simulation and debug tools
His main responsibilities at Siemens include creation of and deployment of verification methodologies,

tool flows and solutions from HDL through to Gates in close collaboration with R & D, Siemens EDA customers and Partners.
Mr Chidolue holds an MSc in Concurrent Engineering of Electronic Product Design from Bournemouth University UK