Alexander Flick develops FPGAs for more than 15 years ranging from logic-only design to Embedded Systems with application specific extensions. He has deployed softcore processors as well as hard-IP ARM controllers in different device families. 

Since 2020 he holds a trainer position at PLC2. His main focus is on the Xilinx tool chaisn for Arm based programmable SoCx / MPSoCs and the new intelligent acceleration concepts coming with the Xilinx Vitis Development Tools.

Andrew Canis manages the software engineering team working on the Smart high-level synthesis software for Microchip's FPGAs. 

He was CEO and co-founder at LegUp Computing, a startup founded in 2015 to commercialize his PhD research on high-level synthesis at the University of Toronto.

LegUp Computing received venture capital funding from Intel Capital in 2018. The company was acquired by Microchip Technology in 2020 to integrate the technology into their FPGA software design suite.

He has co-authored over 10 peer-reviewed research papers focusing on high-level synthesis for FPGAs.

Altaf Khan is the CEO of Infxl LLC, Colleyville, TX. He started his career as an accelerometer system engineer in Silicon Valley, but simplifying neural nets has been his passion over the last three decades. He has developed fast deep nets for real-time applications, low-cost deep nets for battery-operated IoT endpoints, and small-footprint deep nets for FPGA. He has developed intelligent solutions for a major US airline and a well-known auto parts supplier. He has been the CTO of a brokerage company, CEO of two startups, consultant for software process improvement, and an industrial controls engineer. Altaf received his BSEE from Wilkes College, MSEE for the University of Pennsylvania, and PhD from the University of Warwick.

Awanish Verma is Director of strategic and technical marketing in Wired and Wireless business unit in Xilinx, Awanish is responsible for solution architecture of TelcoDC acceleration and Security products for 5G wireless and access networks. Awanish is also responsible for developing networking hardware and software ecosystem and strategic partnerships for FPGA based network interface cards (NICs). Awanish has spent 25 years in networking industry with 20+ years in networking system architecture using FPGAs and ASICs. He has been involved in multiple engineering, solution architecture and marketing roles in multiple networking organizations. He holds BSEE and MSEE with specialization in VLSI and communications.

Baruch works with MathWorks, Germany since October 2016 as a senior application engineer. His main functions include responsibility for HDL code generation and verification tools. 

Prior to joining MathWorks, Baruch was working as an ASIC design and verification engineer, both in Israel and Germany. His main working focus was wireline communication systems as well as memory products.

Baruch has a B.Sc. degree in Electrical Engineering from the Technion, Israel Institute of Technology.

“Dipl.-Ing. (FH) Christian Rudel is working in the semiconductor industry since 20 years. He started his career as System Engineer for TV processors with Philips/NXP,

followed by a Field Application Engineer position for HDMI products with Silicon Image and a hardware development engineer position for FPGA based embedded systems

with Dream Chip Technologies GmbH. In 2018 he joined Microsemi (now Microchip) as Field Application Engineer supporting Field Programmable Gate Arrays (FPGAs) with a focus on industrial embedded vision applications.”

David Kirchner is founder of the Ingenieurbüro David C. Kirchner and since start of this year part of Krassin Consulting GmbH.

After graduating as electrical engineer from the Technical University of Berlin, he started as hardware engineer and is working for over 15 years with FPGAs in various projects and industries.

He is an enthusiastic trainer and teaches as a lecturer at the Beuth University of Applied Sciences.

I am an Associate Director for Systems and Hardware engineering team at Microchip Technology HYD, India. I am responsible for driving system level hardware solutions and architecture for end to end customer applications for High Speed FPGA product families. I also have a strong background in signal-power Integrity, influencing die/package design with respect to SI/PI methodologies and have a proven track record in bringing in customer focus towards defining end system level solutions. I completed my Masters at Santa Clara University, California in VLSI. 

My name is Dirk van den Heuvel (1967). I have an academic degree in electronics engineering and graduated on tool for graphical modelling and code generation of hierarchical state machines for FPGA devices. After having worked for several other design houses, I joined TOPIC Embedded Systems in 2007 as an embedded architect. Most of the (embedded) projects I have been involved with included FPGAs as well as processors/micro-controllers. Last 10 years mostly SOC-type of devices. Applications vary from ppb-accurate VCXO design to multi-stream video processing applications, from medical sensor devices to ultrasound imaging. At TOPIC I co-founded the patented Dyplo® concept, a FPGA-based Network-On-Chip solution wrapping partial reconfigurable functions in a deterministic manner with full Linux software integration. Currently, I am consultant at TOPIC and technically responsible for the premier partnership with Xilinx as well as the System-On-Modules portfolio. 

Information security is my passion since the turn of the millennium and I consider myself a decentralization visionary. With business diplomas plus a doctorate from European Business School (EBS) and a computer science bachelor's degree from James Madison University (USA), I am business-driven yet tech-savvy. Key roles in large-scale infosec projects of global regulated enterprises honed my skills. Since 2013 I am CIO of esatus AG, a consultancy specialized in infosec, headquartered in Rhine-Main close to Frankfurt. I attend to technological innovations via practical and research-driven projects, like the “Secure Platform” initiative which has also spawned the independent expert group “AG Secure Platform”. I am a strong advocate of Simple Secure Computing and Self-Sovereign Identity (SSI). I am board member of TeleTrusT (IT Security Association Germany) for which I chair the “Blockchain” and “Secure Platform” working groups. I am also a Trustee of the Sovrin Foundation and a Steering Committee member of the Trust over IP (ToIP) Foundation.

Dr. Jörg Pospiech graduated in electrical engineering from Ilmenau Technical University in 1991, where he also obtained his doctorate. He then worked at CE-SYS GmbH Ilmenau on electronic mirror replacement systems for vehicles. Since 2003, he has been managing partner of AVT GmbH in Ilmenau, which mainly deals with FPGA design. Due to its FPGA expertise, AVT GmbH was a XILINX Xperts partner and is a member of the Mathworks Partner Programme. The development services implemented range from camera and video technology, measurement technology, cryptography, IP core design to high-quality lighting technology for museums, churches and castles. Development orders from well-known companies from Spartan to Virtex are at the forefront of the activities. Entry-level and special training courses with many practical examples are also offered by Dr. Pospiech.

After graduating from university, Ernst Wehlage started in Darmstadt in the digital development of professional video systems for the future HDTV technology.

In complex systems, FPGA technologies were used early on to achieve the high data rates. These technologies were decisive for the development of new innovative film and video systems in high-resolution real-time processing.

With now 29 years of professional experience in training and application of programmable logic, the fascination of these possibilities is unbroken, as continuously innovative technology leaps provide hardware developers and now also software developers with ever better methods.

Since 2001 he has been a member of the PLC2 team and has been a speaker on almost all topics of PLC2 training courses, designs FPGA-based systems for customers and advises developers on how to solve their development tasks.

Espen is the CEO and founder of the newly established EmLogic and previously also Bitvis, both independent design centres for embedded software and FPGA, - with Bitvis as a leading Nordic company within its field and EmLogic now already well on the way to the same size and position. He graduated from the University of Glasgow (Scotland) in 1987 and has 30 years’ experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway. During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. 

One result of this interest is the UVVM verification platform that is the #1 VHDL verification methodology and library world-wide, and in fact the fastest growing FPGA verification methodology independent of HDL.

He has given many presentations and keynotes internationally on various technical aspects of FPGA development, including lots of hands-on tutorials and presentations at FPGA-Kongress every year since 2016; - all with a crowded audience and great feedback. He is also giving courses world-wide on how to design and verify FPGAs more efficiently and with a better quality.

During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. One result of this interest is the UVVM verification platform that is currently being used by companies world-wide. 

He has given many presentations and keynotes on various technical aspects of FPGA development. He is also giving courses on how to design and verify FPGAs more efficiently and with a better quality. 'Advanced VHDL Verification – Made Simple ' (3 days) and 'Accelerating FPGA design' (2 days) are both arranged in Germany in cooperation with Trias Mikroelektronik. Espen also had a hands-on tutorial and two presentations at FPGA-Kongress in 2016; - both of them with a crowded audience and great feedback on the interesting technical contents.

Harald Werner has over 30 years’ experience in the electronic industry. 

He received an Dipl.- Ing (FH) at the FH Koblenz.

He started his career in 1987 at Siemens AG, in 1992 he joined the EDA industry at Viewlogic Systems in 1995 he started the career in the semiconductor industry at Actel, following in 2000 with Lattice Semiconductor and since 2020 he joined Efinix Inc. as European Sales Director.

Dipl.-Ing. (FH) Jens Hüttemann has over 20 years of semiconductor experience. He started his career in the EDA business working for Mentor Graphics. In 2008 he joined Microsemi as Field Application Engineer supporting a wide range of products with particular emphasis on Field Programmable Gate Arrays (FPGAs).

Prof. Jens Onno Krah studied electrical engineering at the Bergische Universität Wuppertal and received his doctorate in 1993 from Prof. Holtz in the field of electric machine and drive research. Until February 2004, he was responsible for the development of Kollmorgen Servo Drives as technical director. Since 2004, Prof. Krah has been teaching control engineering, motion control, FPGA-based digital signal processing, and functional safety at the TH Köln. 

From April 2014 to March 2017, Prof. Krah took a leave of absence to further develop patents applied for at Beckhoff Automation into products.

The main research interest is the development of robust, energy-efficient, and safe motion control with programmable hardware.

Jim Lewis has over 30 years of design and teaching experience and is well known within the VHDL community. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, networking, fighter jets, video phones, and space craft.

I am a digital design engineer in the Systems Development Group from Analog Devices, Cluj Napoca office Romania for more than three years, cumulating a 15 years of background in digital design and verification.

I am creating reference HDL designs for ADI high speed converters, RF transceiver evaluation boards for Xilinx and Intel platforms and developing the underlaying HDL infrastructure pieces like the JESD interface framework, DMA IPs to support a variety of projects that our group provides. 

Chief Technology Officer at Silexica, Luis manages the company’s technology strategy and assesses new approaches and solutions to democratize accelerated computing. Since 2016 Luis G. Murillo led the core development teams behind the award-winning SLX Tool Suite. Previously, he worked closely with key partners like Ricoh, Fujitsu, Denso, MBDA, and Synopsys, on R&D topics including compilers, debuggers, simulation, high-level synthesis and hardware/software co-design. Before joining Silexica, Luis was a researcher at the Institute for Communication Technologies and Embedded Systems of the RWTH Aachen University (Germany), while pursuing a PhD degree in Electrical Engineering. He also holds a MSc. in Embedded Systems Design from the University of Lugano (Switzerland) and an Electronics Engineer diploma from the University of Antioquia (Colombia).

Dr. Lawrence Spracklen is an experienced leader, with over two decades of experience in developing and delivering cutting-edge solutions. At Numenta Lawrence leads the machine learning architecture team focused on the intersection of AI and hardware. Prior to joining Numenta, Lawrence led research and development teams at several other AI startups; RSquared, SupportLogic, Alpine Data and Ayasdi. Before this, Lawrence spent over a decade working at Sun Microsystems, Nvidia and VMware, where he led teams focused on hardware architecture, software performance and scalability. Lawrence holds a Ph.D. in Electronics Engineering from the University of Aberdeen, a B.Sc. in Computational Physics from the University of York and has been issued over 65 US patents.

Martin Weitzel, born 1954, early interest in electrical engineering (Kosmos "Elektromann") and electronics. At first purely private, thanks to the electronics lab at BASF-Ludwigshafen. Early experiences with digital technology (just search Wikipedia for "SIMULOG").

Abitur 1972, six semesters of studies in electrical engineering, then continued with "technical computer science", both at the "THD" (now: "Technische Universität Darmstadt"). After graduating as "Dipl.-Ing. der Fachrichtung Datentechnik", I immediately went into professional as a software developer/consultant/coach/trainer ... and this now for almost almost 40 years.

Since, without any "fear of contact", I have also occasionally worked on projects in the more business/product management

So I have "seen a lot", but in the end I have always remained - somehow - connected to the "hardware".

Since 2020 he holds a trainer position at PLC2. His main focus is on the Xilinx tool chaisn for Arm based programmable SoCx / MPSoCs and the new intelligent acceleration concepts coming with the Xilinx Vitis Development Tools.

Nick is a Field Application Engineer at Silexica. Since 

2020, he has helped multiple customers make their first 

forays into Vitis HLS, showing them how SLX FPGA can 

assist with synthesizability and optimization of C/C++ 

projects. Before joining Silexica, Nicholas worked in a 

variety of roles within the Xilinx Worldwide Technical 

Support and Cadence Virtuoso Place & Route 

organizations. Nick earned his bachelor's degree in 

Computer Engineering from the University of 

Pittsburgh Swanson School of Engineering.

Pantelis is a Solutions Architect at Silexica. Since 2019, he has helped multiple customers accelerate their datacenter and embedded applications using Vitis/Vivado, showing them how SLX FPGA can assist with synthesizability and optimization of C/C++ projects. Before joining Silexica, Pantelis worked on high-performance computing applications as an ASIC/FPGA front-end hardware and embedded software engineer at Infineon, ARM, and Hyperstone. Pantelis has a master's degree in Electrical and Computer Engineering from the National Technical University of Athens.

Patrick Lehmann studied computer science at Technische Universität Dresden, Germany. He started to teach computer engineering and computer architecture as a tutor. Later on, he specialized in digital design, FPGA technology, and high-speed communication solutions like Serial-ATA, Gigabit Ethernet, or PCI Express. He is now sharing his gained knowledge in labs, research articles, and on social platforms. His research work focused on in-memory database systems, the Serial-ATA protocol implementation and embedding FPGAs into a Cloud infrastructure.

Since 2017, Patrick Lehman is working for PLC2 GmbH as a trainer in the topics of VHDL, OSVVM, FPGA technology as well as PCI Express. In cooperation with PLC2 Design GmbH, he is a developer and team leader in FPGA design projects.

Mr. Lehmann is one of the developers and maintainers of The PoC-Library, a platform and vendor independent open source IP core library. He is also a contributor to the GHDL project, a free VHDL simulator. In 2016, he started an initiative called "Open Source VHDL Group", whose aim is a free collection of VHDL packages. As part of other open source projects, he is steadily promoting the integration of EDA tool and design flows into a collaborative Git environment.

Mr. Lehmann is active in the IEEE P1076 "VHDL Analysis and Standardization Group" since 2014. He detailed and wrote major parts of the language changes for the upcoming VHDL-2018 revision. In 2017, he became an IEEE Standards Association member and was announced vice-chair of the IEEE P1076 working group. In this current work, he is working together with IEEE to release all VHDL language packages as open source, as well as creating a new collaborative, open source publishing flow in IEEE.

Patrick Urban studied applied mathematics and informatics at FH Aachen and computer engineering with specialization in networked and embedded systems at University Duisburg-Essen, Germany.

Since 2012, he is part of the engineering team at Cologne Chip AG and contributes to their latest development, the GateMate FPGA family. In addition to his work in development and technical support, he is the contact person for open source tools.

Puya Amiri is a researcher at the German Research Center for Artificial Intelligence (DFKI) and a PhD student at Saarland University. His research interests include high-performance computing, reconfigurable computing, and signal processing. Before joining DFKI, he was working as a digital design engineer for HW/SW audio platforms. Puya holds a BSc. in computer hardware engineering and received a MSc. in computer science and engineering from Politecnico di Milano on autotuning and optimizations for high-level synthesis and heterogeneous systems.

As the VP of software & AI product management at Xilinx, Ramine Roane is passionate about empowering all developers with the benefits adaptive computing. Ramine joined Xilinx in 2010 and led the introduction of Xilinx’ Vivado Design Suite. Since then he has taken to market higher level design environments such as HLS, Vitis and Vitis AI, enabling software and AI developers. Prior to that, Ramine held roles in management and software architecture in EDA companies as well as FPGA Startups. He holds a Masters in Electronic Engineering and Computer Science from the National Polytechnic Institute of Grenoble, France.

Richard Membarth is a professor for system on a chip and AI for edge computing at the Technische Hochschule Ingolstadt (THI). His research interests include parallel computer architectures and programming models with a focus on automatic code generation for a variety of architectures ranging from embedded systems to HPC installations for applications from image processing, computer graphics, scientific computing, and deep learning.

Richard received the diploma degree in Computer Science from the Friedrich-Alexander University Erlangen-Nürnberg (FAU) and the postgraduate diploma in Computer and Information Sciences from the Auckland University of Technologies (AUT). In 2013, he received the PhD (Dr.-Ing.) degree from FAU on automatic code generation for GPU accelerators from a domain-specific language for medical imaging. After the PhD, he joined the Graphics Chair and the Intel Visual Computing Institute (IVCI) at Saarland University as a postdoctoral researcher. At the German Research Center for Artificial Intelligence (DFKI), he was a senior researcher and team leader for compiler technologies and high-performance computing.

Robin Chacko is working as an AI software developer focusing on the acceleration of Machine learning applications on Xilinx hardware. He holds a master's degree in Mechatronics and his interest in work spans from robotics to its perception using Artificial Intelligence.  Currently, at PLC2 Design, he is responsible for researching and developing AI applications that can levitate the performance benefits of Xilinx FPGA devices. It includes AI model development to its deployment on the hardware. Moreover, he is A Xilinx certified trained for accelerating Machine learning Applications using the Xilinx-Vitis-AI tool chain.

Saad Qazi has a passion for hardware development and FPGAs. Before joining EBV Elektronik GmbH as a Field Application Engineer in 2019, he worked on Hardware development at Denso Automotive and Bosch. He has previous experience with microprocessor design and implementing AI algorithms on FPGAs. Currently, Saad supports many customers across Southern Germany and Austria with organizational, technical, and design issues related to the Xilinx and Microchip FPGAs.

Silviu Adrian Sasu works for ADVA as a Senior Engineer in research and development projects in the Networking Technologies team in Advanced Technology department.

He is responsible for the development and evaluation of architectures, concepts and codes for programmable hardware platforms using low-level and high-level FPGA programming languages for network-wide data-path programmability and edge computing. 

Silviu Adrian Sasu has gained more than 10 years experience as FPGA design engineer, software architect and embedded system developer in various research and product development projects. Broad hands-on experience and knowledge of 5G Ethernet switching

architecture, data plane programmability, low latency and deterministic Ethernet communication, image processing, industrial cameras, and automotive industry.

Sören Heß studied computer science at Technische Universität Darmstadt, Germany.

After the studies he focused on FPGA based vision systems with VHDL and developed vision systems for various segments. Surroundview-systems for heavy duty trucks and machinery, cameras for medicine industry, stereo-cameras for ADAS, autonomous driving and mapping are a part of the product portfolio as well as all kinds of video and interface IP he developed including his teams. Since October 2020 he is technical lead and site owner at PLC2 Design GmbH in Frankfurt and is driving the product and customer developments within his skillset from mechanics over electronics, VHDL, uboot, Linux OS, up to the application including image processing with ROS and dockerization.

In the next couple of years he wants to shape the usage of ROS and AI within the FPGA community.

Graduate engineer, employed for more than 20 years in various positions in the semiconductor industry.

He gained his experience as ASIC and FPGA developer while working on projects for consumer and industrial applications.

Since 2012 working as Field Application Engineer at EBV Elektronik.

Besides various tasks in the field of high-end processing, he focuses especially on projects in the area of machine learning and artificial intelligence. 

2002-2008 Studies at the Technical University of Darmstadt: Micro and Precision Engineering

2008-2011 Technical University of Darmstadt: Research Assistant at the Lighting Technology Department

2011-2012 HTV GmbH Bensheim: Test and Development

since 2012 HTV GmbH Bensheim: Management Assistant

Dipl.-Ing. Thorsten K. Heimann is Chief Financial Officer and Co-Founder at Helion GmbH (a.k.a. HelionVision). He founded Helion GmbH 2003 together with six co-founders as a spin-off company from the Fraunhofer Institute (based on HDR image processing).

Dipl.-Ing. Thorsten Heimann holds the diploma in electrical engineering at the Ruhr-University Bochum.

“Wolfgang Loewer is CTO and Co-Founder of El Camino GmbH. After graduating from the Munich University of Applied Science he started his career as Field Applications Engineer at Altera in 1991. He then Co-Founded El Camino as a design house for programmable logic in 1999 which soon after also specialized in functional verification of ASIC designs.

Wolfgang Loewer has over 30 years of design, consulting and teaching experience in FGPA development and ASIC verification.”