The best, most progressive leaders in the field
Alexander Flick
PLC2
Alexander Flick develops FPGAs for more than 15 years ranging from logic-only design to embedded systems with application specific extensions. He has deployed softcore processors as well as hard-IP ARM controllers in different device families.
Since 2020 he holds a trainer position at PLC2. His main focus is on the AMD tool chain for Arm-based programmable SoCs / MPSoCs and the new intelligent acceleration concepts coming with the AMD Vitis development tools. Currently, he was awarded as number 2 of the AMD top trainers worldwide in 2023.
Alexander Wirthmüller
MPSI Technologies GmbH
Alexander Wirthmueller is a multi-skilled engineer with two decades of experience in solving problems with software. His past projects led him to work with low-level MCU-/FPGA-based electronics and single board computers, all the way to cloud-based scientific simulations. More recently Alexander decided to devote himself to providing the embedded software community with powerful developer tools which eliminate most monotonous aspects of coding. Alexander lives in Munich where he runs MPSI Technologies.
Andreas Kick
Siemens AG
Andreas Kick studied electrical engineering and information technology at OTH Regensburg, specialising in embedded intelligent systems. His master's thesis involved piloting a new technology module for the SIMATIC, in which the integrated FPGA communicates with an optical scan head. In addition to the realisation of FPGA applications, his work at Siemens Customer Service includes embedded software engineering and support for PLC software.
Andreas Schuler
Missing Link Electronics
Andreas Schuler is Director Applications at Missing Link Electronics where he coordinates joint work of Xilinx, customers and MLE. His field of operation reaches over Architecture design, Image processing, Security, Neural Networks to product development.
Andreas Schuler holds a degree in Industrial Electronics (B.Eng.) from Ulm University of Applied Sciences, Germany.
Angelo LoCicero
Intel Deutschland GmbH
Angelo Lo Cicero is Technical Sales Specialist at Intel PSG with special focus on the IoT market and he’s working on FPGA related topics since 2008. He started his career as an hardware designer where he was responsible for designs, integration and verification of several processor based digital designs. Angelo holds a degree from the University of Palermo.
Anton Fogel
Lauterbach GmbH
Anton Fogel
graduated from the University of Heilbronn with a Masters degree in Electrical Systems Engineering and has been working for Lauterbach as a Systems Engineer for 1.5 years. He has experience in hardware-software co-design and has successfully completed numerous projects in this area.
Dr. Aurang Zaib
Microchip Technology GmbH
Dr. Aurang Zaib is a Principal Embedded Solutions Engineer at Microchip Technology Germany GmbH.
He is a seasoned professional with more than 15 years of Industrial and Academic experience of delivering successful projects. Aurang holds a PhD degree from the Technical University of Munich (TUM). He specializes in the areas of Hardware Software Co-design and Machine Learning for Embedded Systems. Before his present engagement, he has been involved in the design and development of complex real time Systems with a strong focus on Image and Video Processing Applications. In his recent assignments, he uses his technical skills and experience to mentor clients
Baruch Mitsengendler
The MathWorks GmbH
Baruch Mitsengendler is a senior application engineer working at MathWorks in Germany since 2016. He provides technical expertise in applying MathWorks capabilities within various HDL-related applications. Prior to joining MathWorks, Baruch worked as an ASIC design and verification engineer, both in Israel and Germany where his focus areas were wireline communication systems as well as memory solutions. Baruch holds a B.Sc. degree in Electrical Engineering from Technion, Israel Institute of Technology
Prof. Dr. Bernhard Lang
Hochschule Osnabrück
Brian Colgan
Microchip Technology GmbH
Brian has many years’ experience in the semiconductor industry, previously working in Xilinx’s research lab; as sales representative for Cypress Semiconductor; and as an FPGA FAE at EPS Global. He is currently a Business Development Manager in the FPGA Business Unit at Microchip Technology where he supports customers throughout Europe. Brian has a Bachelor of Engineering (Honours) in Computer Engineering from the Dublin Institute of Technology (now TU Dublin).
Davide Cieri
Max Planck Institute for Physics
Dr. Davide Cieri is a Staff Scientist at the Max-Planck-Institute for physics in Munich. He is responsible for the upgrade of the first-level muon trigger of the ATLAS experiment at CERN, which operates on Xilinx FPGAs. His mainly contributions are in the development of the reconstruction algorithm and its FPGA implementation. Davide is also passionate about open-source project, and is the author of the widely used tool Hog (HDL-on-git), to manage HDL code on git.
Finally, he chairs the FPGA developers’ Forum (FDF), a common platform to discuss and exchange information, experiences, implementation ideas, tips, and tricks as well as challenges faced with design tools, specific FPGA technologies.
Dimitri Hamidi
The MathWorks GmbH
Dimitri Hamidi is Senior Application Engineer at MathWorks since 2018, with a focus on HDL code generation and verification, as well as signal and image processing. He received a diploma degree in electrical and information technology engineering from the Technical University of Munich. Prior to joining MathWorks, he worked as a research associate at the German Aerospace Center (DLR), served as FPGA engineer at FEI and algorithm engineer at Continental.
Prof. Dirk Koch
Heidelberg University
Dirk Koch leads the Novel Computing Technologies group at Heidelberg University. Before, he worked in the Advanced Processor Technologies Group at the University of Manchester, the University of Oslo, UBC Vancouver, and the University of Erlangen Nuremberg. His main research interests include run-time reconfigurable systems based on FPGAs, embedded systems, computer architecture, VLSI design, and hardware security. Dirk’s group developed the GoAhead tool for implementing partial reconfiguration on FPGAs, the FPGADefender bistream virus scanner, and the FABulous open-source embedded FPGA generation framework. The latter was used to design chips in TSMC and Skywater processes including a memristor (ReRAM) non-volative FPGA. Dirk Koch is the author of the book “Partial Reconfiguration on FPGAs” and a co-editor of the book “FPGAs for Software Programmers”.
Dirk van den Heuvel
Topic Embedded Systems
My name is Dirk van den Heuvel (1967), Principal Consultant at TOPIC. I have an academic degree in electronics engineering and graduated on a tool for graphical modelling and automatic code generation of hierarchical state machines for specifically FPGA devices. After having worked for several other design houses, I joined TOPIC in 2007 as an embedded systems designer. Most of the (embedded) projects I have been involved with use FPGAs as well as application processors or micro-controllers. Applications vary from ppb-accurate VCXO design to multi-stream video processing applications, from medical sensor devices to ultrasound imaging. At TOPIC I co-founded the patented Dyplo® concept, a FPGA-based Network-On-Chip solution wrapping partial reconfigurable functions in a deterministic manner with full Linux software integration. Currently, I am consultant at TOPIC and technically responsible for the premier partnership with AMD/Xilinx as well as the System-On-Modules portfolio of TOPIC.
Dr. Dmitry Eliseev
RWTH Aachen University
Dmitry began his career in 2006 as an electronics developer for scanning probe microscopes. After six years in industry, he started his PhD in engineering at RWTH Aachen University, where he developed electronics and FPGA firmware for acoustic sensors and phased arrays. As a PostDoc at RWTH Aachen, he is currently contributing to the upgrade of the CMS detector at CERN, developing electronics and firmware for the gaseous particle detectors. Dmitry is passionate about FPGAs and SoCs and has a strong interest in silicon photomultiplier-based detectors.
Ernst Wehlage
PLC2
After graduating from university, Ernst Wehlage started in Darmstadt in the digital development of professional video systems for the future HDTV technology.
In complex systems, FPGA technologies were used early on to achieve the high data rates. These technologies were decisive for the development of new innovative film and video systems in high-resolution real-time processing.
With now over 30 years of professional experience in training and application of programmable logic, the fascination of these possibilities is unbroken, as continuously innovative technology leaps provide hardware developers and now also software developers with ever better methods.
Since 2001 he has been a member of the PLC2 team and has been a speaker on almost all topics of PLC2 training courses, designs FPGA-based systems for customers, and advises developers on how to solve their development tasks. He was recently named the number 1 AMD trainer worldwide in 2023.
Espen Tallaksen
EmLogic AS
Espen is the CEO and founder of the newly established EmLogic and previously also Bitvis, both independent design centres for embedded software and FPGA, - with Bitvis as a leading Nordic company within its field and EmLogic now already well on the way to the same size and position. He graduated from the University of Glasgow (Scotland) in 1987 and has 30 years’ experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway. During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement.
One result of this interest is the UVVM verification platform that is the #1 VHDL verification methodology and library world-wide, and in fact the fastest growing FPGA verification methodology independent of HDL.
He has given many presentations and keynotes internationally on various technical aspects of FPGA development, including lots of hands-on tutorials and presentations at FPGA-Kongress every year since 2016; - all with a crowded audience and great feedback. He is also giving courses world-wide on how to design and verify FPGAs more efficiently and with a better quality.
During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. One result of this interest is the UVVM verification platform that is currently being used by companies world-wide.
He has given many presentations and keynotes on various technical aspects of FPGA development. He is also giving courses on how to design and verify FPGAs more efficiently and with a better quality. 'Advanced VHDL Verification – Made Simple ' (3 days) and 'Accelerating FPGA design' (2 days) are both arranged in Germany in cooperation with Trias Mikroelektronik. Espen also had a hands-on tutorial and two presentations at FPGA-Kongress in 2016; - both of them with a crowded audience and great feedback on the interesting technical contents.
Francesco Contu
Avnet EMG Italy Srl (Silica)
Francesco Contu is High Speed and RF System solution Expert for EMEA at Avnet Silica in Milan, Italy.
He has +30 years of experience, his career started at Alcatel (now Nokia) where he architected and designed several mixed signals boards with various interfaces including backplanes, copper and optical links.
He then joined Xilinx where he worked as High Speed IO and then RF Specialist for almost 20 years, before joining Avnet Silica.
He holds a Master in Electronic Engineering form the “Politecnico di Milano” University.
Francisco Perez
Technical Director – EMEA | Future Electronics S.A.
Experienced Design Engineer and System Architect with more than 25 years of industry experience. I’ve worked as Design Engineer and Engineering Manager before switching to technical sales roles as Field Applications Engineer and Solutions/Platform architect.
Fluent building architectures for High Performance and Cloud computing, AI and Video Analytics, and embedded computing platforms including heterogeneous processing and accelerators like CPU, GPU, FPGAs and adaptive SoCs for various markets including video and vision, industrial, healthcare, automotive, military and avionics.
Currently acting as Technical Director – EMEA at Future Electronics.
Hans-Jürgen Schwender
TRIAS Mikroelektronik GmbH
Hans-Jürgen Schwender has a masters degree in electrical engineering. From 1991 until the end of 2001, he worked as an ASIC design engineer at Philips Kommunikationsindustrie and Lucent Technologies in Nuremberg and at Infineon Technologies in San Jose, CA, USA. He worked on the creation of specifications, the implementation in VHDL, verification on module and chip level as well as programming of ASIC Driver Software in C.
Mr. Schwender has been working at TRIAS mikroelektronik GmbH since 2002 and, as the technical manager covers a large part of Siemens EDA's products - with a focus on HDL design, verification and cable harness design products.
Dr. Harald Simmler
Ing. Buero Harald Simmler
Dr. Harald Simmler is the Software Team lead at Hema. In this role, he is responsible for product development and is also driving the innovative Fast-Lane module based automization for more efficient and faster development.
Harald is a FPGA enthusiast working in the FPGA industry for over 20 years in different roles an areas. His PhD about Multitasking on FPGAs was only the starting point for a series of developments in the FPGA domain.
Harald Werner
Efinix GmbH
Over 28 years experience in the FPGA Market
Helmut Demel
Lattice Semiconductor GmbH
At the University of Applied Sciences in Landshut I studied electrical engineering with a special focus on Microelectronics.
There my own FPGA journey started in 1997 using an FPGA device in my thesis work.
Since then, I hold various positions (Application Engineer, Field Application Engineer) at Actel and Lattice Semiconductor, covering mostly the industrial and automotive market.
In my current role as Sr. FAE Manager, I’m in charge of the FAE team in Central Europe and always interested to stay in touch with our customers and partners.
Contact me as well via LinkedIN: https://www.linkedin.com/in/helmut-demel/
Hüseyin Anaç
NCAB Group Germany GmbH
Hüseyin Anaç is a trained electronics technician with over 20 years of professional experience in the electronics sector. He built up his field experience as a technician for packaging machines and later deepened this as a commissioning engineer for wet-chemical systems for the production of photovoltaic cells in the areas of mechanics, electrics, electronics and software. In 2008, he switched to a consulting role as a team leader in component sales. Since 2013, Mr. Anaç has been employed by NCAB Group Germany and has thus been working in the field of printed circuit boards, then as a technician and since 2019 as a Field Application Engineer.
Jens Michaelsen
Avnet Silica
Jens Stapelfeldt
AMD
Jens works as AI Business Development Manager for AMD in Europe. He has more than 25 years of design, training and development experience in the microelectronics and semiconductor industry. Before joining AMD as part of the Xilinx acquisition, Jens hold several positions in technical support and Business Management (Technical Sales Lead Europe at Xilinx, Senor FAE at Texas Instruments 5 years and Business Manager and ARM Architecture Trainer at Doulos 10 years).
In addition to a degree in microelectronics engineering (FH Oldenburg / Wilhelmshaven) and Uni Manchester UK, Jens completed 2018 a part-time MBA in International Marketing and Business Management with a Master Thesis around AI/ML in the Semiconductor and researched and analysed more than 600 AI/ML start-ups in Europe.
Happy to connect via LinkedIn and talk about AI/ML and find innovative solution with AMD / Xilinx technology.
www.linkedin.com/in/jensstapelfeldt
Jim Lewis
SynthWorks Design Inc
Jim Lewis has over 30 years of design and teaching experience and is well known within the VHDL community. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, networking, fighter jets, video phones, and space craft.
Joachim Goertz
3M
Joachim studied electrical engineering at the University of Applied Science (FH) Aachen. After his graduation in 1999, Joachim joined 3M as Application Engineer. Since that time he supports customers across EMEA on 3Ms Interconnect Product Portfolio (cables, connectors and cable assemblies).
Joachim Müller
Efinix Inc.
Upon graduating at TU Braunschweig in 1989, Joachim Müller held positions in ASIC development, sales and marketing, before joining Lattice Semiconductor in October 2000 as Senior FAE. Since October 2021 he is in charge of Field Application, Europe, for Efinix Inc.
Jorge André Gastmaier Marques
Analog Devices Inc.
Jorge is a Digital Design Engineer at Analog Devices Inc.
He works on FPGA design, and Linux and baremetal (no-OS) driver development, with the intention of providing full stack open-source solutions to interface ADI's parts.
He holds a B.Sc. in Electrical Engineering from the Federal University of São Carlos and is currently pursuing his master's degree at the University of São Paulo.
Previously, he researched embedded computer vision in the space & defense field, and he shifted his career to working on reference designs to better fit his advocacy for open-source solutions.
Dr. Jörg Pospiech
AVT GmbH Ilmenau
He studied electrical engineering at the Technical University of Ilmenau, where he also obtained his doctorate in the field of lightning protection. His doctoral work was flanked by patent applications and the development of a new product for the company Dehn SE.
He was then employed by CE-SYS GmbH Ilmenau as a development engineer for mirror replacement systems with FPGAs. Since 2004 he was in parallel active as managing director of AVT GmbH. He took over this activity completely from 2008 and has also been the sole shareholder since 2020. In the course of this time many customer projects with FPGAs were successfully developed. With the company motto "Solving the impossible" these orders and further research achievements were also always of a high standard.
Already in 2004 the first small FPGA development kit was manufactured in AVT and the first IP cores were created. With the latest developments we enter a new phase of collaborative DevKit development, which will be presented.
Kamil Rudnicki
Brightelligence sp. z o.o.
Kamil is co-owner of Brightelligence sp. z o.o., Poland. Apart from managing the company and projects, he performs research and development in the field of FPGAs across many applications like SDN, SDR, video conversion and HPC. During his 16-year-long FPGA journey, he participated in several high-profile projects. His professional interest focuses on optimization and complex system debugging - "a needle in a haystack."
He received his MSc from Lodz University of Technology, Poland, in 2008, and his Ph.D. from the University of Glasgow, UK, in 2014. His cientific background helps him succeed in challenging commercial projects. In his free time, he enjoys cycling and horse-riding.
Klaus Kohl-Schöpe
Arrow Central Europe GmbH
Klaus Kohl-Schoepe is a Technology Field Application Engineer (FAE) covering the Central European region. He started in 1986 as a developer of measurement systems. In 1998 he switched to distribution and work as FAE at Silica, Rutronik and now for 16 years at Arrow. He supports all topics related to MCU/DSP/MPU including processor IP, associated software and IDE, memory, wired connectivity, safety, and security.
Marco Höfle
Avnet EMG AG
Marco Höfle, born in 1978, lives with his family in Switzerland and is employed by Avnet Silica. He supports customers in southern Germany, Switzerland and Austria. His tasks include customer consulting, customer-specific trainings as well as customer support in their development with Xilinx products.
The Big "X" runs through his entire professional career, starting with his diploma thesis, technical support at Xilinx in Dublin, development management in an engineering office and since May 2018 as Embedded Specialist Xilinx SoC at Avnet Silica.
Marco Smutek
Arrow Central Europe GmbH
Marco Smutek is a Technology Field Application Engineer (FAE) covering Switzerland and Southwest Germany. Having started his career at Xilinx in 2004, he joined PLC2 as a trainer before accepting his position as FAE at Arrow in 2014. He supports all topics related to FPGAs from Altera and Microchip.
Martin Kellermann
Microchip Technology GmbH
Martin Kellermann is a Marketing Manager at Microchip Technology GmbH, Munich. Earlier he was a Staff Field Application Engineer at Xilinx. He is a seasoned FPGA and SoC professional with a track record of successful customer and project engagements in the industrial, automotive, and data-center domains. He possesses a strong background in high-speed serial data transmission, signal integrity and hardware debugging which helped numerous customers finish their designs successfully. He has also taught courses covering industrial applications and hardware concepts. Martin is a graduate of the Landshut University of Applied Sciences.
Mathias Sandner
Lauterbach GmbH
Mathias Sandner
graduated from the Technical University of Munich with a Master's degree in Electrical Engineering and a minor in Computer Science. He has been working as a full-stack developer and system engineer for Lauterbach for the last 8 years. He has experience with numerous debug and trace interfaces used in the industry, in particular the implementation of the hardware and software on the tool side of these interfaces.
Michael Hutchison
Senior Director - Customer Experience Engineering, Software and Solutions | AMD
Michael Hutchison, senior director at AMD, is an industry veteran with more than 20 years of experience architecting, developing, and building leading-edge FPGA and adaptive SoC products for markets including automotive, consumer, and test & measurement. Michael leads the Customer eXperience Engineering, Software, and Solutions teams. This role encompasses driving the AMD Vivado™, Vitis™, Vitis AI, System Software, and IP solutions to meet customers’ needs. He is also responsible for ensuring that AMD adaptive SoC and FPGA products have a full solution stack available to enable customers in today's complex development environments. Michael holds a Bachelor of Applied Science in Computer Engineering from Simon Fraser University, holds seven patents, and has lived and worked in Germany and Canada throughout his career.
Michal Pacula
Aldec, Inc.
Michal Pacula, Technical Support Manager, over 25-year experience in FPGA/SoC, joined Aldec in 1998 and worked in a wide range of positions that include Application Engineer and SQA Manager responsible for Active-CAD, Active-HDL and Riviera-PRO products. Michal’s practical experience includes Digital Design, Verification Methodologies, Linting and a deep understanding of HDL modeling. Michal graduated with M.S. in Electronic Engineering (EE) at the Silesian University of Technology in Gliwice, Poland.
Nikolai Krassin
PLC2
Nikolai studied Embedded Systems Engineering in Freiburg.
He's been working as a Trainer at PLC2 since 2010 for the following topics:
Developing projects using FPGAs, MPSoCs and VHDL.
Oliver Bründler
Enclustra GmbH
Expert in FPGA/SoC design with 13 years of experience in digital signal and video processing on FPGA. Received a BSc degree in microelectronics in 2009 from the technical college FHNW, Switzerland. Worked at Paul Scherrer research institute in Switzerland, developing electronics for particle accelerators. Currently at Enclustra, where he spent 11 years as an FPGA/SoC system designer and project manager, working on customer design projects.
Oren Hollander
HandsOn Training Inc.
Oren Hollander has over 20 years of FPGA, ARM, Security design & training experience.
Oren is an Intel, ARM, NXP, ST, NewAE, eShard, and Microchip authorized trainer.
Oren trained over the years thousands of engineers around the world in FPGA design, Arm architecture, security for Embedded systems & FPGA security.
He trains the top noche silicon vendors such as Apple, Samsung, Marvell, NXP, Intel, Broadcom, Microchip to name a few, so his knowledge is always one step ahead of the general market.
Oren specialized in the military field as well, and works as senior consultant to the top notch military companies in Israel and abroad.
Oren works closely with the silicon vendors and security researchers to bring the latest and greatest know-how and experience to the market.
Patrice Brossard
Future Electronics S.A.
After obtaining degree at the French “Paris Orsay University”, I spend almost 10 years designing ASIC at the company Bull then 2 years at a car manufacturer working on automotive electronic network.
Since the years 2000, I’m working in the electronics component distribution environment. I have been working now for more than 15 years at Future Electronics supporting and promoting FPGA technologies with a new role of Vertical Segment Manager in charge of Programmable Logic for 3 years now.
Passionate about new electronic technologies and always be on the lookout for the needs of the new applications in order to address the markets of the future.
Patrick Lehmann
PLC2
Patrick Lehmann, a graduate of computer science from Technische Universität Dresden, Germany, embarked on his journey in computer engineering and architecture as a tutor. Over time, his focus shifted towards digital design, FPGA technology, and high-speed communication solutions such as Serial-ATA, Gigabit Ethernet, and PCI Express.
With a passion for sharing knowledge, Patrick actively engages in teaching, research, and social platforms. His research endeavors span diverse areas including in-memory database systems, Serial-ATA protocol implementation, and the integration of FPGAs into Cloud infrastructure.
Since 2017, Patrick has been an integral part of PLC2 GmbH, where he serves as a trainer specializing in VHDL, OSVVM, FPGA technology, and PCI Express. His dedication and expertise led him to his current role as the Head of System Engineering at PLC2 Design GmbH since 2023.
Patrick Lehmann's contributions extend beyond the confines of his workplace. He is a developer and maintainer of the PoC-Library, an open-source IP core library that transcends platforms and vendors. Additionally, he actively contributes to the GHDL project, a renowned free VHDL simulator. Notably, in 2016, he initiated the "Open Source VHDL Group," aiming to create a comprehensive collection of VHDL packages freely accessible to all.
Patrick is deeply engaged in standards development, notably within the IEEE P1076 "VHDL Analysis and Standardization Group" since 2014. His significant involvement includes detailing and drafting substantial portions of the language changes for the upcoming VHDL-2018 revision. Recognized for his contributions, Patrick was appointed as a vice-chair of the IEEE P1076 working group in 2017. Presently, he collaborates with IEEE to release all VHDL language packages as open source, while also spearheading efforts to establish a new collaborative, open-source publishing flow within IEEE.
Patrick Urban
Cologne Chip AG
Patrick Urban studied applied mathematics and informatics at FH Aachen and computer engineering with specialization in networked and embedded systems at University Duisburg-Essen, Germany.
Since 2012, he is part of the engineering team at Cologne Chip AG and contributes to their latest development, the GateMate FPGA family. In addition to his work in development and technical support, he is the contact person for open source tools.
Stanislaw Klinke
EBV Elektronik GmbH & Co. KG
Graduate engineer, employed for more than 20 years in various positions in the semiconductor industry.
He gained his experience as ASIC and FPGA developer while working on projects for consumer and industrial applications.
Since 2012 working as Field Application Engineer at EBV Elektronik.
Besides various tasks in the field of high-end processing, he focuses especially on projects in the area of machine learning and artificial intelligence.
Ted Speers
Head of Product Architecture and Planning, Technical Fellow | Microchip Technology Inc.
Ted Speers is a Technical Fellow at Microchip’s FPGA BU, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. Ted is a RISC-V leader and evangelist and has served on the Board of Directors of RISC-V International since its inception in 2016. He joined Actel (now part of Microchip) in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is co-inventor on 35 U.S. patents. In his role, Ted has consistently defined first of it’s kind products, the most recent example being PolarFireSoC, the first RISC-V based SoC FPGA. Prior to joining Actel, he worked at LSI Logic. Ted has a Bachelor of Science in chemical engineering from Cornell.
Thomas Zerrer
Smartlogic GmbH
Thomas Zerrer studied electronic engineering and received a „Dipl. Ing“ degree from the University of Stuttgart in 1994. Active in the field of PCI and PCI Express since 2002. Founded Smartlogic GmbH in 2005 as owner and CEO. Main activity is the definition and development of DMA IP Cores.
Tom Richter
The MathWorks GmbH
Tom Richter joined MathWorks in Germany 2011 and worked 10 years as a Training Engineer for Model Based Design, Signal Processing, Communications, and Code Generation. With a strong focus on ASIC and FPGA design, he also developed training courses for HDL code generation and HW/SW co-design.
Since 2021, Tom works as an Application Engineering Specialist for HDL and System-on-Chip. Tom has a Master of Engineering degree from the University of Ulster in Belfast and a Diploma of Electrical Engineering from the University of Applied Sciences in Augsburg.
Udo Blaga
Avnet Silica
Udo Blaga, in the business for more than 20 years is employed by Avnet Silica Germany. He is member of the Avnet Silica Power team; these three people supporting customers in Switzerland, Germany and Austria. His tasks include product presentation, customer-specific trainings as well as customer support in their development with power products.
Wolfgang Loewer
El Camino GmbH
Wolfgang Loewer is CTO and Co-Founder of El Camino GmbH. After graduating from the Munich University of Applied Science he started his career as Field Applications Engineer at Altera in 1991. He then Co-Founded El Camino as a design house for programmable logic in 1999 which soon after also specialized in functional verification of ASIC designs.
Wolfgang Loewer has over 30 years of design, consulting and teaching experience in FGPA development and ASIC verification.
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