Program 2020*

Tuesday, September 29, 2020

8:40 AM
Welcome by the organizers
Speaker: Michael Eckstein | Vogel Communications Group GmbH & Co. KG

Redaktion EP - Vogel Communications Group GmbH & Co. KG

Speaker: Stefan Krassin | PLC2 GmbH

Already in the beta phase of the first ZYNQ-7000 SoC generation in 2010, Stefan Krassin trained far more than 500 developers in this area in Europe. He has gained practical experience through many successful customer developments. Furthermore, Stefan Krassin is the first officially certified trainer in Europe for the next generation Zynq UltraScale+ MPSoC.

TRACK 1 IN THE MORNING

9:00 AM

Track 1 in the morning
09:00 a.m.: Targeting Motor Control Algorithms and Interface IP to SoC FPGAs (45 min) more
Today’s motor control systems are combining control algorithms and interfaces to PWM, ADC, and encoders. Also networking technologies like Ethernet, EtherCAT, and Profilink in industrial applications, or CAN/CANFD in automotive applications are relevant. FPGAs with hardened embedded microprocessors on a single chip (SoC FPGAs) have been proven as a technology that smartly supports
such applications. Model-based design and automated code generation for C and HDL code can be used to deploy the algorithms to the processor and to the FPGA. Using the IP core generation workflow, pre-developed interface IP can be added to the reference design and connected to the algorithmic blocks. Finally, the microprocessor peripherals provide a wide range of communication interfaces to external or on-board components.
This presentation shows the design of a complete model in the MATLAB and Simulink environment, the generation of C and HDL code, and the deployment to a prototyping platform. The design is targeted to a Xilinx Ultrascale+ SoC board and a power electronics board, both developed from Trenz Electronic and
supported by a BSP from MathWorks. The multi domain model includes those main functionalities:
  • position and velocity control algorithm for implementation on the ARM processor
  • the field-oriented control algorithm for implementation on the FPGA
  • a plant model of the power electronics and the motor and load for physical simulation
  • stimuli to test the design in simulation and drive the motor on the prototyping platform
The presentation also demonstrates what effects of the power electronic and the motor can be incorporated in the model and how well the physical model in simulation follows the real motor behavior
Speaker: Dr. Werner Bachhuber | The MathWorks GmbH

Dr.-Ing. Werner Bachhuber works as an application engineer at MathWorks and is responsible for code generation and verification of ASICs, FPGAs and SoCs, as well as for signal processing and communication technology. During his research and industrial activities he developed ASICs and ASSPs for high data rate telecommunication networks and supported customers in the application of complex FPGA designs. Dr.-Ing. Werner Bachhuber received his doctorate at the Technical University of Munich in the field of integrated circuits.

09:45 a.m.: Setup and Configuration of a completely customizable n-channel power sequencer based on FPGA (45 min) more
In this course you will learn how to setup and configure an n-channel power sequencer.  You will take advantage of the easily configurable Quartus Platform Designer GUI coupled with the pin flexibility of an FPGA to provide a completely customizable power sequencer solution for any multi-rail device.  While providing ultimate flexibility, this solution is also cost advantageous and has the ability to include other features such as temperature / fan speed monitoring and reset sequencing.  This design fits best with the feature set of Intel Max10 CPLD family. We will provide a short overview on the intel Max10 CPLD family. In addition, an introduction to scalable digital multi-phase solutions for high current core power will be provided. 
Speaker: Giuseppe Privitera | Intel Deutschland GmbH

Giuseppe serves as Business development for EMEA and North America for Intel Enpirion Power Solution BU inside PSG. His focus are customers, establishing and maintaining effective relationships he earns their trust taking care of every aspect of the relationship to deliver the best possible experience. He joined Intel in 2016 and prior to it he served in the semiconductor supplier’s space covering many positions as Application Manager, Product Marketing manager and Business Development. His technical experience spans in the fields of Analog, Power and Mixed Signals ICs. Giuseppe received his master’s degree in Electronic Engineering at University of Catania (Italy) and he is currently enrolled in the Executive MBA 2021 at IESE Business School in Munich. In his free time Giuseppe likes to spend time with his family and friends cooking his special low ’n slow Texan style BBQ.

10:30 a.m.: Break-Out with partners
11:00 a.m.: Multi-clock switching in SoC implementation in ASIC and FPGA (45 min) more
As the technology evolves and new tasks for System-on-Chips inspire stable grow of complexity
and extension of application areas, the early silicon validation and software development efforts
become a real challenge. FPGA devices are the perfect solution nowadays to implement
SoC/MPSoC, and they also are well-proven for ASIC prototyping. Many SoC in mobile or multipower-
source applications use different clocks for the core system operation in different modes
interchangeably. It means, the system core should be able to switch between them safely, while
providing constant data and operation integrity. Besides, the ASIC production flow requires
support of the special scan/test functionality for silicon wafers, which are not used in FPGA
device by default, but should be verified for the ASIC prototype. The solution to the problem of
the clock switching implementation in ASIC and FPGA RTL-code is addressed in the article.
Natural difference between ASIC and FPGA clock resources makes the direct usage of the ASIC
RTL version in the FPGA impossible. The article presents the scheme, based on the complex
mode-driven system clock synchronization principle.
A single valid system clock for the complete SoC based on the stable fast running clock source is
described. Core clock enable signals are defined for each operation mode and take into account
asynchronous clock domains crossings. Integrity and spike-less operation of system clock is
ensured by the proper hand-shaking and synchronization.
The VHDL description for ASIC-product and FPGA-prototype is synthesizeable by the respective
tools and represent exactly correct simulation behavior.
The provided clock switching structure is scalable and may include any number of required
clocks.
The method was successfully implemented in several real industrial ASIC designs and FPGAbased
emulation hardware.
Speaker: Dr. Oleg Rudakov | PLC2 GmbH

Oleg has started with ASIC and FPGA design EDA in 1995. He has successfully completed Ph.D. thesis on special sensitivity analysis of testability of analog ASICs using artificial intelligence methods in 1999. Since 2000 Oleg worked as RTL verification engineer, designer, project lead, technical manager for world-know semiconductor companies. His technical and business knowledge are now available as he holds a position of a trainer/designer at PLC2 GmbH. Oleg specializes in hardware systems architecture and production using Xilinx and Lattice devices. The Oleg’s presentation will give you a real-life example of the multiple external clocks switching and RTL code unification for ASIC/FPGA product development.

11:45 a.m.: Next Generation Memory for FPGAs (45 min) more
DDR5 as next generation memory significantly increases performance @ lower power consumption. It also brings more flexibility with up to 8 bank groups and reliability with on Die ECC. The innovations that led to the high performance of DDR5 are expained and layout recommendations are given.  
Speaker: Gerhard Risse | Arrow - Micron Semiconductor (Deutschland) GmbH

After finishing his studies after 9 semesters in Electrical Engineering at the Technical University of Karlsruhe, Gerhard went to Brazil to design SDH Telecom Equipment. Back in Germany, worked as Field Application Engineer in industrial network companies such as Moxa and semiconductor companies such as Intel, Infineon and finally Micron. Gerhard got 15 patents granted mainly in memory technology and network technology.

TRACK 2 IN THE MORNING

9:00 AM

Track 2 in the morning
09:00 a.m.: A RISC-V in 1000 Lines of VHDL more
Structure of the intended talk:
  • Short introduction of the speaker
  • What is RISC-V?
    • Market environment of the RISC-V.
    • Licensing of the RISC-V ISA – in relation to ARM
    • Core Instruction Set and optional Extensions.
  • How to implement a CPU in the classic way
    • Classic CPU design with separated datapath and controller.
  • Implementing a CPU as a FSMD (FSM with an implicit datapath)
    • Outline of the FSMD concept.
  • Comparison of the two concepts
    • Optimization possibilities in the datapath and the controller. Focusing on resource sharing of manual implementations and resulting area reductions.
    • Flexibility for future extensions and adaptions.
    • Strength of the FSMD concept in terms of code length.
    • Readability and easy understanding of a FSMD implementation. This is the main target of this implementation.
    • Easy and fast debugging due to little code length.
  • Concept of my implementation
    • A complete CPU within two VHDL processes. One register process and one combinatorically process.
    • Complete register set as a record type.
    • Basic resources of this CPU implementation and actions during instruction processing.
  • § Address progression
  • § Status flags and their administration
  • § Memory
  • § Register set
    • Usage of special FPGA resources (Block RAM) and its integration into the FSMD concept.
  • Explanation of the instruction set implementation in my design based on some instructions.
    • ADD: A very simple register-based instruction which is very common.
    • LOAD/STORE: Accessing external memory via the Avalon-Memory-Mapped-Bus.
    • JAL/JALR: Jump with link register. Frequently used for function calls.
    • A more complex instruction.
  • Comparison of the synthesis results with common implementations
    • Further comparison of my design before and after optimizations with respect to chip area and maximum clock frequency.
  • Verification methods used to verify my design.
  • How to get access to my design.
Speaker: Alexander Binder | Fachhochschule Oberösterreich

Alexander Binder is a Hardware and Software Engineering student at the University of Applied Sciences in Upper Austria. He finished his Bachelor of Science degree this summer and has been working with Hardware Simulation and Synthesis Tools since he started at the university back in 2016. He is very interested in the concepts and internals of modern processors and therefore decided to design an own implementation of a RISC-V CPU.

09:45 a.m.: UVVM – All the new stuff for this standardised VHDL verification methodology more
Improve your FPGA quality *and* reduce your verification workload – only by making more structured testbenches. The open source UVVM has the most extensive VHDL verification support available and lets you verify really complex DUTs in a very efficient manner with excellent testbench overview.
UVVM has been significantly updated through the European Space Agency’s UVVM extension project. We have previously released the Scoreboard, and now lots of other new functionality has also been added. The most important of these are activity watchdog, Error injection, Monitor, Hierarchical VVCs and Specification Coverage. This presentation will go through all new features and explain how they will help you making a better testbench and develop this much faster.
Speaker: Espen Tallaksen | Bitvis AS

Espen Tallaksen is the managing director and founder of Bitvis, an independent design centre for embedded software and FPGA. He graduated from the University of Glasgow (Scotland) in 1987 and has 30 years’ experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway, including his earlier founded company Digitas. During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. One result of this interest is the UVVM verification platform that is currently being used by companies world-wide. He has given many presentations and keynotes on various technical aspects of FPGA development. He is also giving courses on how to design and verify FPGAs more efficiently and with a better quality. 'Advanced VHDL Verification – Made Simple ' (3 days) and 'Accelerating FPGA design' (2 days) are both arranged in Germany in cooperation with Trias Mikroelektronik. Espen also had a hands-on tutorial and two presentations at FPGA-Kongress in 2016; - both of them with a crowded audience and great feedback on the interesting technical contents.

10:30 a.m.: Break-Out with partners
11:00 a.m.: Functional Safety in FPGAs - shortening development time for functional safe systems with changing requirements (45 min) more
The development of todays electronic systems is quite challenging to cope with changing requirements.
Especially when it comes to functional safety, flexible and scalable concepts can help to add more features like extended safety functions, new connectivity and security for next generations needs.
This talk gives an introduction into functional safety in different application areas and typical safe development flows. It discusses different safety concepts and shows industrial and automotive application- and implementation examples. And it talks about the advantages in using FPGAs for your safe and future proof development.
Speaker: Harald Friedrich | NewTec GmbH

1983 - 1986: Berufsakademie Stuttgart – Studium Elektrotechnik/Nachrichtentechnik

1986 - 1995: Entwicklungsingenieur im Bereich Telekom und Industrie

1995 - 2017: verschiedene Rollen in der Elektronik Distribution in Applikation, Marketing und Management, u.a. für prog.Logik, Functional Safety, MicroProzessoren

seit 2017: freiberuflich selbständig: “Harald Friedrich TecConsult”, u.a. für Fa. NewTec

11:45 a.m.: Architectural Consideration for Functional Safety in Xilinx devices (45 min) more
As system requirements are getting more and more complex, including network based systems such as IOT, the program developer faces higher demands and functional safety guarantees can only be defined in a specific context.
In this session we describe how the Xilinx SoC/MPSoC technologies can meet these requirements,
if the developer even knows how to use its appropriate methods.
When safety requirements can not be achieved globally, isolation is one of the decisive methods both in the hardware layer and in the context of programming.
Proof of functional safety requires extensive test scenarios: On the vendor side for the silicon chip, for the developer in the booting context, at run-time for several simultaneous running processes - all this requires additional processes.
Xilinx provides solutions and methods in this regard, which we will show here.
Speaker: Ernst Wehlage | PLC2 GmbH

After graduating from university, Ernst Wehlage started in Darmstadt in the digital development of professional video systems for the future HDTV technology. In complex systems, FPGA technologies were used early on to achieve the high data rates. These technologies were decisive for the development of new innovative film and video systems in high-resolution real-time processing. With now 29 years of professional experience in training and application of programmable logic, the fascination of these possibilities is unbroken, as continuously innovative technology leaps provide hardware developers and now also software developers with ever better methods. Since 2001 he has been a member of the PLC2 team and has been a speaker on almost all topics of PLC2 training courses, designs FPGA-based systems for customers and advises developers on how to solve their development tasks.

12:30 PM
Break
12:45 PM
Couch Talk
1:30 PM
Keynote: Enabling Smart and Secure Embedded Designs with Low Power FPGAs more
Device developers in a wide range of markets, including industrial and automotive, are looking for quick and easy ways to add support for AI, embedded vision and hardware security features to their products. This creates design challenges as such devices often need to meet strict power, thermal and design footprint requirements.
A compelling hardware platform for adding processing and hardware security to embedded devices are secure, small form factor, low power FPGAs. As they process data in parallel, they can deliver the necessary processing performance at very low power (measured in milliwatts). And as FPGAs are often the first on/last off device in a system, they are the ideal hardware platform for establishing a system-level Root of Trust that can confirm all system components are operating securely.
In his keynote presentation, Lattice Semiconductor’s Esam Elashmawi will highlight how the latest FPGAs from Lattice enable low power data processing and system security for applications like AI and embedded vision processing. Additionally, Esam will touch on how Lattice also offers developers complete solutions stacks (comprehensive hardware, software and IP bundles) to simplify and accelerate the integration of such emerging technologies to new or existing product designs.

Speaker: Esam Elashmawi | Lattice Semiconductor

Esam Elashmawi is Lattice Semiconductor’s Chief Marketing and Strategy Officer. He joined Lattice in September 2018 after serving as Senior Vice President and General Manager at Microsemi Corporation since 2010. Esam brings to the role 30 years of FPGA technology and industry experience. Over the past decade, he has successfully managed and developed solutions and equipment for the datacenter, automotive, defense, communications and industrial markets. He most recently served as Senior Vice President and General Manager at Microsemi Corporation since 2010. Esam previously served as Vice President of Product Development at Actel Corporation, which Microsemi acquired in 2010. Earlier in his career he co-founded SiliconExpert Technologies, a component management software company, which was acquired by Arrow Electronics. Esam holds a Master of Science in Electrical Engineering and a Bachelor of Science in Electrical Engineering from Santa Clara University.

TRACK 1 IN THE AFTERNOON

2:00 PM

Track 1 in the afternoon
02:00 p.m.: Demystify AC power delivery – reduce EMI issues (45 min) more
Fast switching needs power supply with low inductance/impedance. Modern FPGAs switch at hundreds of MHz to GHz and need the corresponding AC current supply.
Vendor guidelines give an idea of how many and witch types of decap should be used and which target impedance has to be achieved.
A proper PCB layout is the key to deliver the AC power to the FPGA and herby to success.
There are various schools of thought of how to realize the power stack, the decap strategy and plane capacitors.
Simulation is the best tool to develop the right PCB design for a given application and get it first time right. In this presentation the strategy will be demonstrated on the core power rail of a FPGA compute module. 
Speaker: Ronald Weber | CADFEM GmbH

Seit mehr als 25 Jahren im Bereich des PCB Layouts in der Dienstleistung tätig. Mehrjährige Stationen bei IBM, Intel, Infineon. Die letzten 7 Jahre hauptsächlich im Bereich Simulation und Messung von Signal und Power Integrität. Seit 2,5 Jahren bei CADFEM als „Begeisterer“ für Simulation

02:45 p.m.: Designing with RF Data Converters (45 min) more
This presentation discusses the design process for RF data converters. Live demos present the IP configuration, simulation and implementation. Finally, an implemented design will be validated on real hardware.
Speaker: Dr. Jürgen Wolde | Ingenieurbüro Wolde

Jürgen Wolde studied Theoretical Electrical Engineering at today's Technical University of Ilmenau and graduated as Dipl.-Ing. in 1984. In 1989, he received his doctorate in the field of electromagnetic compatibility at today's University of Applied Sciences in Mittweida. The field of activity ranged from ASIC design for products, to component design and complex research patterns in which FPGA-based circuit boards with 10Gbit/s interfaces were used. Collaboration in various studies and research projects up to 100 Gbit/s as well as management activities completed the range of applications.

3:30 p.m.: Break-Out with partners
04:00 p.m.: Interfacing High-Speed ADC (45 min) more

This presentation describes the procedure for the development, verification and timing specification for a typical high speed ADC Interface.  During the presentation the device AD9252 will be used for reference.

The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. Operating at a conversion rate of up to 50 MSPS, it is optimized for performance and low power in applications where a small package size is critical. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO)  for capturing data on the output and a frame clock (FCO) for signalling a new output byte are provided. 

After the definition of general requirements (basic specification), a precise definition of timing and functional requirements for the interface to be implemented is derived based on data sheets provided by the ADC component vendor.

The resulting hierarchical block diagram serves as the basis for development and simulation of the ADC interface. After describing the sub-modules or the complete ADC interface, the corresponding simulation model for the ADC component is developed. Based on ADC interface and the ADC   simulation model, a complete Test Bench is built to be used during functional simulation/verification.  After functional verification, the previously defined timing constraints are entered and used for the physical implementation

Speaker: Eugen Krassin | PLC2 GmbH

Dipl.Ing. Eugen Krassin completed his studies of electrical engineering at the University of Stuttgart. He then worked as an electronics developer for well-known companies before he founded the engineering office PLC2 Eugen Krassin which was renamed PLC2 GmbH in 2007. Dipl.-Ing. Eugen Krassin was established by Xilinx as one of the first ATPs (Authorized Training Provider) in the German-speaking world and is the author of several different training courses and workshops as well as technical articles on the use of FPGAs.

04:45p.m.: Interfacing High-Speed DAC (45 min) more

This presentation describes the procedure for the development, verification and timing specification for a typical high speed DAC Interface.  During the presentation the device LTC2000A will be used for reference.

The LTC®2000A is a family of 16-/14-/11-bit 2.7Gsps current steering DACs. The single (1.35Gsps mode) or dual (2.7Gsps mode) port source synchronous LVDS interface supports data rates of up to 1.35Gbps using a 675MHz DDR data clock, which can be either in quadrature or in phase with the data. An internal synchronizer automatically aligns the data with the DAC sample clock. Additional features such as pattern generation, LVDS loop out and junction temperature sensing simplify system development and testing. A serial peripheral interface (SPI) port allows configuration and read back of internal registers.           

 

After the definition of general requirements (basic specification), a precise definition of timing and functional requirements for the interface to be implemented is derived based on data sheets provided by the DAC component vendor.

The resulting hierarchical block diagram serves as the basis for development and simulation of the DAC interface. After describing the sub-modules or the complete DAC interface, the corresponding simulation model for the DAC component is developed. Based on DAC interface and the DAC simulation model, a complete Test Bench is built to be used during functional simulation/verification. After functional verification, the previously defined timing constraints are entered and used for the physical implementation

Speaker: Eugen Krassin | PLC2 GmbH

Dipl.Ing. Eugen Krassin completed his studies of electrical engineering at the University of Stuttgart. He then worked as an electronics developer for well-known companies before he founded the engineering office PLC2 Eugen Krassin which was renamed PLC2 GmbH in 2007. Dipl.-Ing. Eugen Krassin was established by Xilinx as one of the first ATPs (Authorized Training Provider) in the German-speaking world and is the author of several different training courses and workshops as well as technical articles on the use of FPGAs.

TRACK 2 IN THE AFTERNOON

2:00 PM

Track 2 in the afternoon
02:00 p.m.: Partially Constrained Record Types in VHDL-2008 (45 min) more
  • Key points:
    •  unconstrained / partially constrained types (records, arrays) from VHDL-2008
    • Infere constraints from init value. See LCS-2016-019
    •  Mode Views from VHDL-2019
    • How to use this approach for building generic modules(auto-adapting to different interface sizes)
  • Description:
Since VHDL-2008, VHDL offers a technique to define record types for data busses like AXI4, WishBone or Avalon that do not need to know how many bits will be used for address or data signals. This feature is called *partially constrained types*. Using this technique, can speed up development time by reducing code lines, complexity and increasing readability as well as maintainability.
 
In this talk, I'll present how to use records to describe complex bus interconnects like AXI4 and how to size these records, using initializer functions or package instantiations. These unconstrained records can also be used for describing all kinds of configuration data structures used at elaboration time for inferring hardware.
 
In the second half of my talk, I'll show how this approach can be improved with the latest VHDL-2019 feature named *mode views*. In short, *mode views* define an overlay of direction for every element in a record type. New attributes will ease the usage of mode views. 
Speaker: Stefan Unrein | PLC2 GmbH

Stefan has studied Electrical Engineering/ Information Technology in University of applied Science Offenburg. In his Master Thesis at PLC2 GmbH he created a high-speed UDP-Ethernet IP Core. After his Thesis he stayed at PLC2 and is here working as FPGA Developer specialized in Multi-Gigabit Transceivers and High-Speed Protocols like PCIe and Multigigabit Ethernet. Since then he had the technical project lead for several Customer projects.

02:45 p.m.: VHDL-2019 - The New Stuff (45 min) more
With almost 3 years delay, VHDL-2019 has been finally released on 23.12.2019. It bring lots of nice additions.
Some a minor language enhancements, some bring new functionality and others are complete new concepts
in VHDL.

This talk will present new attributes, mode views and enhanced type generics.
Speaker: Patrick Lehmann | PLC2 GmbH

Mr. Patrick Lehmann studied computer science at Technische Universität Dresden, Germany. He started to teach computer engineering and architecture as a tutor in his 3rd year. Later on he specialized in digital design, FPGA technology, and high speed communications. He shared his gained knowledge in labs, in research articles, and on social platforms. His research focuses on digital design with VHDL as well as the integration of EDA design steps into a Git and web services based development flow.
Mr. Lehmann is one of developers and maintainers of The PoC-Library, a platform and vendor independent open source IP core library. He is also a contributor to the free VHDL simulator GHDL. In 2016, he started an initiative called "Open Source VHDL Group".
Mr. Lehmann is active in the IEEE P1076 "VHDL Analysis and Standardization Group" since 2014. He detailed and wrote major parts of the language changes for the upcoming VHDL revision. In 2017 he became an IEEE Standards Association member and was announced vice-chair of the P1076 working group.
Since June 2017, Mr. Lehmann got employed by PLC2 GmbH as a developer and trainer.

3:30 p.m.: Break-Out with partners
04:00 p.m.: Accelerating Verification Model development using OSVVM's common transactioninterfaces more
In OSVVM, a Transaction-based Model is an entity and architecture that receives abstract transaction information via a transaction interface and then dispatches one or more sequences on the model interface or interfaces to execute the transaction.
There are three steps required to create an OSVVM Transaction-based Model:
  • Create the record which communicates transaction information from the test sequencer to the model
  • Create the transaction procedures to initiate transactions in the models
  • Create the transaction-based model
Transaction interfaces allow us to take a step back and look at an interface more abstractly. For example, from a transaction level, when we send data on a UART interface or send data on an AxiStream interface, there is little difference – only the width of the data word. Similarly, when we do write transaction on an AXI interface and a write transaction on an X86 interface, they both transfer write address and data.
OSVVM's common transaction interfaces define a record with which to communicate and transaction procedures to initiate transactions.
As model developers, if we can use one of the OSVVM defined common transaction interfaces, then all we need to do is write the model itself. This allows us to focus on writing just model behavior.
As test developers, if a model has used one of the OSVVM defined common transaction interfaces and we have used a different model that uses the same OSVVM common transaction interface, then we already know the basic transaction API for the interface. This makes writing tests easier. It also facilitates porting tests from one interface to another.                                                                  

Presentation Ordering:
This presentation is a companion presentation to the other OSVVM presentations. It would be better if it was offered after the Better FPGA Verification with OSVVM and before the Tutorial Getting Started with the OSVVM Verification IP Library.
Speaker: Jim Lewis | SynthWorks Design Inc.

Jim Lewis has over 30 years of design and teaching experience and is well known within the VHDL community. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, networking, fighter jets, video phones, and space craft.

04:45 p.m.: Continuous Integration and Beyond: Managing Complex FPGA Designs (45 min) more
For many years, the continuous increase of transistor integration on silicon wafers has allowed engineers to design increasingly powerful hardware year after year. Nowadays even small teams of engineers can build powerful digital systems using modern FPGAs and the tools built around them. While this increase in feasibility allows developing products and solving problems not possible even a few years back, it also comes with an increased complexity of digital designs that both tools and engineers need to be able to handle. The term “design productivity gap” has commonly been used to discuss the apparent mismatch of developer and tool productivity as compared to the possibilities offered by current manufacturing technologies.
This talk seeks to discuss numerous state-of-the-art techniques borrowed from software engineering and their application to modern FPGA designs, using freely available tools (git, GHDL, vUnit, …) and concepts (semantic versioning, unit testing, continuous integration) with examples focusing on Xilinx FPGAs.
It starts out with introducing common topics such as configuration management, version control and versioning schemes, as well as prerequisites and implementation of automated unit and regression testing using appropriate abstraction levels. It is discussed how these principles can allow greater flexibility during design space exploration while increasing an engineer’s trust in their own design, benefitting both junior and senior developers.
Secondly, these basics are used to discuss possible continuous integration and delivery (CI/CD) flows and how automated and reproducible builds can increase productivity for both digital designers and firmware engineers. Finally, an exemplary project targeting a Xilinx FPGA including both digital hardware implemented in Vivado as well as software and driver components utilizing the Vitis SDK is introduced to demonstrate these concepts and how they apply to different developers and parts of a project. Additionally, guidelines on version control for projects using Vivado and Vitis are given, extending those published in Xilinx user guides.
Speaker: Jakob Winkler | Silicon Austria Labs GmbH

Silicon Austria Labs GmbH

5:30 PM
Final Note Day 1
Speaker: Michael Eckstein | Vogel Communications Group GmbH & Co. KG

Redaktion EP - Vogel Communications Group GmbH & Co. KG

Speaker: Stefan Krassin | PLC2 GmbH

Already in the beta phase of the first ZYNQ-7000 SoC generation in 2010, Stefan Krassin trained far more than 500 developers in this area in Europe. He has gained practical experience through many successful customer developments. Furthermore, Stefan Krassin is the first officially certified trainer in Europe for the next generation Zynq UltraScale+ MPSoC.

Wednesday, September 30, 2020

8:45 AM
Introduction Day 2
Speaker: Michael Eckstein | Vogel Communications Group GmbH & Co. KG

Redaktion EP - Vogel Communications Group GmbH & Co. KG

Speaker: Stefan Krassin | PLC2 GmbH

Already in the beta phase of the first ZYNQ-7000 SoC generation in 2010, Stefan Krassin trained far more than 500 developers in this area in Europe. He has gained practical experience through many successful customer developments. Furthermore, Stefan Krassin is the first officially certified trainer in Europe for the next generation Zynq UltraScale+ MPSoC.

TRACK 1 IN THE MORNING

9:00 AM

Track 1 in the morning
09:00 a.m.: Artificial Intelligence - Success Stories and Limits, Risks and Opportunities (90 min) more
Artificial Intelligence - Success Stories and Limits, Risks and Opportunities

  • Success stories
  • Methodological foundations: machine learning and combinatorial optimization
  • Where are the limits?
  • Opportunities for the industry
  • Potential risks
Speaker: Prof. Dr. Bernhard Nebel  | Universität Freiburg

Universität Freiburg

10:30 a.m.: Break-Out with partners
11:00 a.m.: Light Neural Network based Industrial Defect Detection on Lattice ECP5 FPGA (45 min) more
A vast majority of industries world-wide still rely on manual inspection as part of their overall Quality Assurance (QA) process. This includes human operators performing manual eyeballing or touch based inspection of objects-under-manufacture. Assembly line efficiencies can be significantly improved if defect detection on these parts can be automated. Deployment of Vision based inspection systems have been limited by platform costs which is largely a function of the compute power required to run complex Image Processing algorithms and Deep Learning models. This paper introduces a practical implementation of Industrial Defect Detection using Light Neural Networks that can run on low cost FPGAs. These custom built Neural Nets are optimized layer by layer such that 100% of the inference is executed purely in hardware. Results from an actual implementation on a low-cost Lattice ECP5 FPGA achieving greater than 95% defect classification accuracy on gears at 30+ frames per second is demonstrated. These custom Light Neural Nets are built to effectively leverage the capabilities of Lattice’s hardware Machine Learning Engine. It is anticipated that this solution will enable wider adoption of fully automated Vision-based anomaly detection, allowing factories of tomorrow to adhere to the tenets of Industry 4.0.
Speaker: Sujith Mathew Iype | Ignitarium

Sujith Mathew Iype is the Cofounder and CTO of Ignitarium Technology Solutions Pvt Ltd and is responsible for driving innovation and nascent technology adoption at Ignitarium. During his career Sujith has worked as an architect for ASICs and FPGA based systems for consumer electronics and healthcare applications. He was responsible for building a focus for Ignitarium in Artificial Intelligence and targeting them to cost effective hardware platforms.

11:45 a.m.: Create highly flexible and future-proof AI solutions (45 min) more
Develop highly flexible and future-proof AI solutions with reconfigurable & adaptable AI engines for any kind of machine learning.
Clarification of AI solutions for Edge, Cloud and On-Premises with Xilinx Vitis AI development stack for AI inference with details of use case examples for video surveillance and automotive.
Speaker: Michael Uyttersprot | Avnet Europe Comm. VA

Michaël Uyttersprot is a European Technical Manager for Avnet Europe Comm. VA and an expert in Embedded Vision. He has a strong expertise in imaging, processing, computer vision and deep learning.

TRACK 2 IN THE MORNING

9:00 AM

Track 2 in the morning
09:00 a.m.: General purpose FPGA with novel architcture (45 min) more
Summary:
A new family of FPGAs called GateMateTM is introduced with some unique features. The FPGAs uses a novel programmable Element with 8 logic inputs. A novel routing structure with so called double checkerboard architecture is used.
Three different application modes are provided (low power, economy and speed)
  • Logic capacity from 40.000 to more than a million LUT-4 equivalent cells.
  • Novel architecture with new programmable element (CPE)
  • CPE has LUTtree with 8 inputs.
  • 3 application modes (low power, economy, speed)
  • Only 2 signal layers on PCB necessary
  • Low configuration bit count
  • Very fast configuration using 4 bit SPI interface up to 100 MHz
  • No excessive start-up currents
  • Only two supply voltages needed, which can be applied in any order
  • Multiple clocking schemas
  • Dual ported Block RAMs with 1-80 bit data width, also configurable as FIFO
  • Multipliers with arbitrary factor width implementable, so addressing the needs for DSP and KI applications
  • SERDES 2.5 Gb/s
  • General Purpose IOs (GPIO) configurable as single-ended or differential
  • Pullup/Pulldown resistors configurable
  • Support for ADC and DAC with additional IP cores
  • Core voltage depending on application mode: 0.9 V, 1.0 V, 1.1 V
  • EasyConvertTM software to migrate existing designs to GateMateTM
  • Fast GateMateTM Place&Route with automatic clock Skew analysis and fixing
  • Static Timing Analysis for performance evaluation Low Power 28 nm SLP GlobalfoundriesTM process technology, made in Germany.
Speaker: Dr. Michael Gude | Cologne Chip AG

Michael Gude achieved a Diploma and Dr. degree from the University of Aachen (RWTH) in electrical engineering. He was involved in research and development from the early days of microprocessors. Michael is founder and CEO of several technology oriented companies; one of them Cologne Chip AG, which was started in 1995. Already in 1989 Michael used the first FPGAs from Actel. Cologne Chip is well known for telecommunication chips since more than 20 years. Now offering their latest developments, the GateMate FPGA family. Michael holds a bunch of patents all over the world.

09:45 a.m.: Architectures for FPGA-based Applications – A Software-based Approach (45 min) more
This seminar – scheduled for about 45 minutes including questions – attempts to find similarities in the software design for FPGAs, compared to software design and architectures for microprocessor-based development. FPGA-based and µP-based computing differ by some (hardware) architectural facts but show also similarities. Therefore the goal is to migrate well-known architectures (from software world) into the FPGA world to define systematic architectural concepts.
For this purpose some approaches in software architecture are transformed to examples in VHDL/FPGA and discussed. Furthermore, the approaches are discussed concerning their practability.
Speaker: Prof.-Dr. Christian Siemers | TU Clausthal

Christian Siemers was born in Kiel in 1954. He completed his studies in physics and mathematics at the Christian-Albrechts-University of Kiel and graduated in 1981 with a diploma in physics and in 1984 with a doctorate in natural sciences. He then worked for Siemens Daten- und Kommunikationstechnik in Munich, and in 1989 he moved to Dräger Medizintechnik, Lübeck. Seit 1993 arbeitet er als Professor für Technische Informatik, zunächst an der Fachhochschule Stralsund (bis 1995), danach an der Fachhochschule Westküste in Heide/Holstein (bis 2001). Seit 2002 ist er an der Hochschule Nordhausen, seit 2008 auch an der Technische Universität Clausthal tätig. Dort vertritt er die Professur für Automatisierungstechnik (zu 50%). Seine Hauptinteressen gelten einerseits programmierbaren Systemarchitekturen, spezifisch Mikroprozessoren und programmierbaren Logikbausteinen sowie allen Übergangsformen, andererseits dem Hardware/Software-Interface, den Konzepten zur Programmentwicklung und den Programmiersprachen. Aktuelle Themen sind Transcodierung zwischen Programmiersprachen, schnelle Echtzeitsysteme sowie In-Situ-Monitoring (Fehlerdetektierung zur Laufzeit).

10:30 a.m.: Break-Out with partners
11:00 a.m.: Speed-dating Lattice latest evaluation boards, demonstrators, demo/reference designs (45 min) more
  • You have new requirements for your products and question how feasible these are to implement with traditional components (mcu, asp)
  • You wonder if FPGA technology could assist your project needs, short and long term.
The last few quarters Lattice has announced various new HW families, as well as an enhanced SW engine. During this technical session, Christian will dive into our latest Lattice solutions by:
  • providing you guidelines to quickly find the right evaluation boards for your feasibility studies
  • guide you through our most relevant demo’s and reference designs, all to assist you with been able to implement, verify your project within short time windows. 
Speaker: Christian Michel | Lattice

Christian Michel is a Senior Field Application Engineer at Lattice Semiconductor. Based out of the Company's German office, Mr. Michel supports Lattice's low power, low cost and small form factor FPGA solutions and works closely with customers throughout Europe. Mr. Michel is a seasoned engineer with over 25 years of experience in ASIC and FPGA technologies.

11:45 a.m.: On the development of FPGAs according to DO254 (45 min) more
Abstract: The authors give an overview of developments of FPGAs according to avionics functional safety standard DO-254. They give insight into their experience with FPGA designs ranging from DAL D to DAL A, including development process from requirements capture to verification and audits with certification authorities. The presentation is divided into two parts. The first part provides information on the development process, while the second part concentrates on practical aspects of design, verification and documentation. Several presented principles are also applicable to functional safety in automotive or industrial projects.
Speaker: Eugen Krassin | PLC2 GmbH

Dipl.Ing. Eugen Krassin completed his studies of electrical engineering at the University of Stuttgart. He then worked as an electronics developer for well-known companies before he founded the engineering office PLC2 Eugen Krassin which was renamed PLC2 GmbH in 2007. Dipl.-Ing. Eugen Krassin was established by Xilinx as one of the first ATPs (Authorized Training Provider) in the German-speaking world and is the author of several different training courses and workshops as well as technical articles on the use of FPGAs.

Speaker: Dr.- Ing. Steffen Zimmermann | PLC2 GmbH

Steffen looks back on a 23 year career in Consumer and Avionics industries from sensor signal processing hardware and software development to management in engineering and certification of Avionics products. He joined PLC Design GmbH as general manager due to the excellent cooperation he experienced with Eugen Krassin’s PLC2 during two DO254 DAL-C and DAL-A certification projects involving FPGAs for complex signal processing in digital sensor control loops. He knows the inherent conflicts between the goals of quick development towards a “functional” solution and the development process required to develop a functionally safe hardware design. Steffen’s part of the presentation will give hints on DO254 standard reading and he will describe how the DO254 standard can be adopted by engineers as a truly helpful resource to develop a functionally safe product.

12:30 PM
Break
12:45 PM
Couch Talk
1:30 PM
Keynote: Democratizing Accelerated Computing
Speaker: Maximilian Odendahl | Silexica GmbH

Maximilian Odendahl is on a mission to democratize accelerated computing, enabling intelligent electronic products of the future. He is the CEO and co-founder of Silexica and has built the company from its beginning in 2014 to become a global leader in software design automation for heterogeneous computing. Silexica now has a team of 60 people and has raised $28m from leading international VCs. He was selected as Germany's Top 40 under 40 in 2019. Max received a Computer Engineering diploma from RWTH Aachen University in 2010 and was formerly the Chief Engineer of the Chair for Software for Systems on Silicon leading 15 research assistants. His work has been published in over 20 publications in international computing conferences and journals.

TRACK 1 IN THE AFTERNOON

2:00 PM

Track 1 in the afternoon
02:00 p.m.: Accelerate HLS Design Space Exploration with SLX FPGA (45 min) more
High Level Synthesis is a powerful engine for exploring trade-offs between performance and area when implementing algorithms for execution on FPGAs. Generating this type of data, however, requires a deep understanding of where opportunities for parallelism exist in the algorithm, and a highly iterative flow of providing compiler directives for exploring different implementations.
SLX FPGA is a tool that sits on top of HLS compilers.  It can take in the source code and automatically insert compiler directives.  It’s deep profiling capability, coupled with constraints-based heuristics and platform models enable it to perform a much deeper design space exploration than possible by manual methods, in a fraction of the time.
The constraint-based flow provides insights on how resources can incrementally be consumed to exploit more of the parallelism inherent in the algorithm. In the end, an area/performance graph can be plotted to satisfy designers wishing to perform early design evaluations, final production optimization or device selection for IP re-use across multiple products.  
Speaker: Stephane Gauthier | Silexica GmbH

Stephane’s passion for using FPGAs to accelerate compute intensive tasks has led him to be a Product Manager at Silexica. With a career that spans nearly 30 years in engineering, sales and product management across a variety of markets and applications, he is currently focused on helping designers maximize productivity and performance when implementing C/C++ algorithms on FPGAs. Stephane’s presentation will describe how SLX FPGA empowers new and advanced HLS users to be successful in optimizing their designs by providing deep code insights, automatic parallelism detection and fast design space exploration.

02:45 p.m.: A new methodology for insights and optimization assistance for HLS designs (45 min) more
In this presentation we will present a methodology for speeding up FPGA design with High-level Synthesis (HLS). We will illustrate how this design methodology using a tool, SLX FPGA, can be used to produce FPGA designs with similar performance to an HDL implementation, within weeks instead of months.

HLS enables FPGA design speedup by an order of magnitude compared to low-level HDL implementation. HLS uses a C/C++ executable definition of the application to generate hardware. The power and flexibility of HLS comes from its ability to implement the same algorithm using different pragmas to guide the implementation architecture. This necessarily leads to different performance/area trade-offs which can be leveraged to better satisfy application needs. To really harness this power, the FPGA designer needs to understand the effect of each of line of C code in order to determine which pragmas to use, where to insert them, and what parameters should be set for each one.

SLX FPGA is an optimization tool that sits on the top of HLS. It performs deep static and dynamic analysis of the C/C++ code to understand how to best optimize the design, and then automatically generates and inserts the necessary pragmas. It also provides other useful insights to the user like parallelism analysis, dependency analysis, memory usage analysis etc. These insights can be invaluable for determine if and where code refactoring can help to further optimize the implementation.

We will demonstrate the effectiveness of this methodology on an image processing application. We will see how SLX FPGA automatically generates pragmas that lead to a highly optimized implementation, and how it provides insights to enable the FPGA designer to further optimize results. Furthermore, we will see how by applying simple modifications in the C code of the algorithm we can obtain results with SLX FPGA and HLS similar to hand-optimized implementation with significantly less effort.
Speaker: Philippe Manet | Embedded Computing Specialists Sprl

Embedded Computing Specialists Sprl

3:30 p.m.: Break-Out with partners
04:00 p.m.: Image considerations for AI systems (45 min) more
Image processing topic is becoming more and more a trend topic.
What are the key parameters designing an imaging system considering AI?
Are you familiar with Shutter performance, Dynamic Range, Optics and resolution? Different applications different sensors?
Speaker: Giulio Spinelli | Avnet EMG Italy Srl (Silica)

Business Development and Technology Specialist for Sensing and Timing EMEA Based in Milano , Italy. Giulio brings decades years of successful experiences at European level in Sales, Application, R&D and Team Management

04:45p.m.: Image Recognition using Deep Learning on FPGAs & SoCs (45 min) more
Designing Deep Learning networks for embedded devices like FPGAs and SoCs is challenging because of resource constraints, complexity of programming in Verilog or VHDL, and the hardware expertise needed for prototyping on an FPGA or SoC device.
Starting with a pre-trained model, either trained in MATLAB or any framework of your choice, we demonstrate a workflow for deploying the trained network from MATLAB to a standard SoC board. In this presentation we are showing the workflow for an image recognition application.
Deep Learning algorithm engineers can quickly explore different networks and their performance on an FPGA or SoC directly from MATLAB. The workflow also enables hardware engineers to optimize and generate portable Verilog and VHDL Code that can be integrated with the rest of their application.
Speaker: Baruch Mitsengendler | The MathWorks GmbH

Baruch works with MathWorks, Germany since October 2016 as a senior application engineer. His main functions include responsibility for HDL code generation and verification tools. Prior to joining MathWorks, Baruch was working as an ASIC design and verification engineer, both in Israel and Germany. His main working focus was wireline communication systems as well as memory products. Baruch has a B.Sc. degree in Electrical Engineering from the Technion, Israel Institute of Technology.

TRACK 2 IN THE AFTERNOON

2:00 PM

Track 2 in the afternoon
02:00 p.m.: Vitis - The Unified Software Platform as a High End Application Acceleration Platform (45 min) more

Vitis™ integrates CPU code with FPGA kernels to accelerate FPGA development with High level Languages. The Vitis platform helps to develop, compile and debug applications and devise acceleration kernels suitable for the specific algorithm at hand.

This presentation will provide a walkthrough to offload functions to FPGA/CPU starting from a host side description. It will show that the deployment and tooling supports Edge systems and data center targets likewise. Based on this understanding examples of readily available acceleration kernels will be touched.

Speaker: Alexander Flick | PLC2 GmbH

Alexander develops FPGAs for more than 15 years ranging from logic-only design to Embedded Systems with application specific extensions. He has deployed softcore processors as well as hard-IP ARM controllers in different device families. Since 2020 he holds a trainer position at PLC2. His main focus is on the Xilinx tool chaisn for Arm based programmable SoCx / MPSoCs and the new intelligent acceleration concepts coming with the Xilinx Vitis Development Tools.

02:45 p.m.: Introduction to Vitis AI – unified development environment for AI inference (45 min) more
Vitis AI is unified AI Platform which allows development for both cloud and edge applications.
In this session participants can learn how Vitis AI supports mainstream frameworks and the latest models capable of diverse deep learning tasks.
All the powerful components of Vitis AI will be explained in the details:
  • Quantizer that supports model quantization, calibration, and fine tuning
  • AI Optimizer that can prune the deep learning model
  • Profiler, which provides layer by layer analysis to help with computation bottlenecks
  • AI library offers unified high-level C++ and Python APIs for maximum portability from edge to cloud
  • Comprehensive set of pre-optimized models that are ready to deploy on Xilinx devices

There will be also architecture and adoption of Deep Learning Processor Unit (DPU) presented.
After that session, participants should be able to understand how to implement trained deep learning model into Xilinx device with support of Vitis AI design flow.
Speaker: Stanislaw Klinke | EBV Elektronik GmbH & Co. KG

Graduate engineer, employed for more than 20 years in various positions in the semiconductor industry. He gained his experience as ASIC and FPGA developer while working on projects for consumer and industrial applications. Since 2012 working as Field Application Engineer at EBV Elektronik. Besides various tasks in the field of high-end processing, he focuses especially on projects in the area of machine learning and artificial intelligence.

3:30 p.m.: Break-Out with partners
04:00 p.m.: Xilinx Versal, the first Adaptive Compute Acceleration Platform (45 min) more
Introduction to the new 7nm fully software-programmable heterogeneous compute platform. This new category of devices allows users to customize their own domain-specific architecture. It combines Scalar Engines, Adaptable Engines and Intelligent Engines to achieve high performance improvements compared to the existing CPU or FPGA implementations. Especially interesting for Data Center, wired network, 5G wireless, and automotive driver assist applications.

After that session, participants should be able to understand how the ACAP architecture significantly extends the capabilities of programmable logic alone by combining the hybrid of programmable logic, scalar-, adaptable- and intelligent Engines.
Speaker: Saad Qazi | EBV Elektronik GmbH & Co. KG

Saad Qazi has a passion for hardware development and FPGAs. Before joining EBV Elektronik GmbH as a Field Application Engineer in 2019, he worked on Hardware development at Denso Automotive and Bosch. He has previous experience with microprocessor design and implementing AI algorithms on FPGAs. Currently, Saad supports many customers across Southern Germany and Austria with organizational, technical, and design issues related to the Xilinx and Microchip FPGAs.

04:45 p.m.: Faster Multi-Port Memory Accesses with Xilinx' Versal NOC (Network on Chip) (45 min) more
A higher demand on parallel processing like in MPSoC technologies leads to more memory bandwitdh and is typically limited at the global accessible shared DDR memory. The latest Versal ACAP architectures introduces Programmable Network on Chip (NOC). NoC provides an optimized multi-terabit interconnect between the different compute engines and integrated IP blocks present
in the Versal ACAP architecture, simplifying timing closure and saving logic resources. The NoC compiler provides a streamlined programming experience while allowing users to manage latency and QoS, ensuring that critical data paths are prioritized and even run-time configurable.
Speaker: Ernst Wehlage | PLC2 GmbH

After graduating from university, Ernst Wehlage started in Darmstadt in the digital development of professional video systems for the future HDTV technology. In complex systems, FPGA technologies were used early on to achieve the high data rates. These technologies were decisive for the development of new innovative film and video systems in high-resolution real-time processing. With now 29 years of professional experience in training and application of programmable logic, the fascination of these possibilities is unbroken, as continuously innovative technology leaps provide hardware developers and now also software developers with ever better methods. Since 2001 he has been a member of the PLC2 team and has been a speaker on almost all topics of PLC2 training courses, designs FPGA-based systems for customers and advises developers on how to solve their development tasks.

5:30 PM
Final Note Day 2
Speaker: Michael Eckstein | Vogel Communications Group GmbH & Co. KG

Redaktion EP - Vogel Communications Group GmbH & Co. KG

Speaker: Stefan Krassin | PLC2 GmbH

Already in the beta phase of the first ZYNQ-7000 SoC generation in 2010, Stefan Krassin trained far more than 500 developers in this area in Europe. He has gained practical experience through many successful customer developments. Furthermore, Stefan Krassin is the first officially certified trainer in Europe for the next generation Zynq UltraScale+ MPSoC.

*Subject to changes

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